MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 16

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

List of Figures
Technical Data
16
14-3 8-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . . . 227
14-4 16-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . . 228
14-5 Block Diagram for Port7 with Output compare /
14-6 C3F-C0F Interrupt Flag Setting . . . . . . . . . . . . . . . . . . . . . . .229
15-1 Multiple Serial Interface Block Diagram . . . . . . . . . . . . . . . . . 264
15-2 Serial Communications Interface Block Diagram . . . . . . . . . . 265
15-3 Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . . . 277
15-4 SPI Clock Format 0 (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . 278
15-5 SPI Clock Format 1 (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . 279
15-6 Normal Mode and Bidirectional Mode. . . . . . . . . . . . . . . . . . . 280
16-1 MI Bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
16-2 Biphase coding and error detection . . . . . . . . . . . . . . . . . . . . 292
16-3 MI BUS Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
16-4 A typical MI Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
17-1 The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
17-2 User Model for Message Buffer Organization. . . . . . . . . . . . . 308
17-3 32-bit Maskable Identifier Acceptance Filters . . . . . . . . . . . . . 312
17-4 16-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . . 312
17-5 8-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . . . 313
17-6 SLEEP Request / Acknowledge Cycle . . . . . . . . . . . . . . . . . . 319
17-7 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
17-8 Segments within the Bit Time . . . . . . . . . . . . . . . . . . . . . . . . . 323
17-9 msCAN12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
17-10 Message Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . . 325
17-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
17-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
18-1 Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . 350
19-1 BDM Host to Target Serial Bit Timing. . . . . . . . . . . . . . . . . . . 381
19-2 BDM Target to Host Serial Bit Timing (Logic 1) . . . . . . . . . . . 381
19-3 BDM Target to Host Serial Bit Timing (Logic 0) . . . . . . . . . . . 382
20-1 Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
20-2 POR and External Reset Timing Diagram . . . . . . . . . . . . . . . 415
20-3 STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 416
20-4 WAIT Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 417
20-5 Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
20-6 Port Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .419
20-7 Port Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .419
Pulse Accumulator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
List of Figures
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor