MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 219

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PWCTL — PWM Control Register
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
RESET:
Bit 7
0
0
6
0
0
The value in each duty register determines the duty of the associated
PWM channel. When the duty value is equal to the counter value, the
output changes state. If the register is written while the channel is
enabled, the new value is held in a buffer until the counter rolls over or
the channel is disabled. Reading this register returns the most recent
value written.
If the duty register is greater than or equal to the value in the period
register, there will be no duty change in state. If the duty register is set
to $FF the output will always be in the state which would normally be the
state opposite the PPOLx value.
Left-Aligned-Output Mode (CENTR = 0):
Duty cycle = [(PWDTYx + 1) / (PWPERx + 1)] × 100%
Duty cycle = [(PWPERx−PWDTYx)/(PWPERx+1)]×100% (PPOLx = 0)
Center-Aligned-Output Mode (CENTR = 1):
Duty cycle = [(PWPERx−PWDTYx)/PWPERx]×100%
Duty cycle = [PWDTYx / PWPERx] × 100%
Read and write anytime.
PSWAI — PWM Halts while in Wait Mode
CENTR — Center-Aligned Output Mode
To avoid irregularities in the PWM output mode, write the CENTR bit
only when PWM channels are disabled.
0 = Allows PWM main clock generator to continue while in wait
1 = Halt PWM main clock generator when the part is in wait mode.
0 = PWM channels operate in left-aligned output mode
1 = PWM channels operate in center-aligned output mode
5
0
0
mode.
Pulse Width Modulator
PSWAI
4
0
CENTR
3
0
RDPP
2
0
PUPP
1
0
PWM Register Description
Pulse Width Modulator
PSBCK
Bit 0
0
(PPOLx = 1)
(PPOLx = 0)
(PPOLx = 1)
Technical Data
$0054
219