MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 23

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Technical Data — MC68HC912D60A
1.1 Contents
1.2 Introduction
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
1.2
1.3
1.4
1.5
1.6
The MC68HC912D60A microcontroller unit (MCU) is a 16-bit device
available in two package options, 80-pin QFP and 112-pin TQFP. On-
chip peripherals include a 16-bit central processing unit (CPU12), 60K
bytes of flash EEPROM, 2K bytes of RAM, 1K bytes of EEPROM, two
asynchronous serial communication interfaces (SCI), a serial peripheral
interface (SPI), an enhanced capture timer (ECT), two (one on 80QFP)
8-channel,10-bit analog-to-digital converters (ATD), a four-channel
pulse-width modulator (PWM), and a CAN 2.0 A, B software compatible
module (MSCAN12). System resource mapping, clock generation,
interrupt control and bus interfacing are managed by the lite integration
module (LIM). The MC68HC912D60A has full 16-bit data paths
throughout, however, the external bus can operate in an 8-bit narrow
mode so single 8-bit wide memory can be interfaced for lower cost
systems. The inclusion of a PLL circuit allows power consumption and
performance to be adjusted to suit operational requirements. In addition
to the I/O ports available in each module, 16 (2 on 80QFP) I/O port pins
are available with Key-Wake-Up capability from STOP or WAIT mode.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Devices Covered in this Document. . . . . . . . . . . . . . . . . . . . . . 24
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
General Description
Section 1. General Description
Technical Data
23