MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 241

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TFLG1 — Main Timer Interrupt Flag 1
TFLG2 — Main Timer Interrupt Flag 2
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
RESET:
RESET:
Bit 7
C7F
Bit 7
TOF
0
0
C6F
6
0
6
0
0
TFLG1 indicates when interrupt conditions have occurred. To clear a bit
in the flag register, write a one to the bit.
Use of the TFMOD bit in the ICSYS register ($AB) in conjunction with the
use of the ICOVW register ($AA) allows a timer interrupt to be generated
after capturing two values in the capture and holding registers instead of
generating an interrupt for every capture.
Read anytime. Write used in the clearing mechanism (set bits cause
corresponding bits to be cleared). Writing a zero will not affect current
status of the bit.
When TFFCA bit in TSCR register is set, a read from an input capture or
a write into an output compare channel ($90–$9F) will cause the
corresponding channel flag CnF to be cleared.
C7F–C0F — Input Capture/Output Compare Channel “n” Flag.
TFLG2 indicates when interrupt conditions have occurred. To clear a bit
in the flag register, set the bit to one.
Read anytime. Write used in clearing mechanism (set bits cause
corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR
register is set.
C5F
5
0
5
0
0
Enhanced Capture Timer
C4F
4
0
4
0
0
C3F
3
0
3
0
0
C2F
2
0
2
0
0
C1F
1
0
1
0
0
Enhanced Capture Timer
Bit 0
Bit 0
C0F
0
0
0
Timer Registers
Technical Data
$008E
$008F
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