MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 252

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Capture Timer
ICSYS — Input Control System Control Register
Technical Data
252
RESET:
SH37
BIT 7
0
SH26
6
0
An IC register is empty when it has been read or latched into the holding
register.
A holding register is empty when it has been read.
NOVWx — No Input Capture Overwrite
SHxy — Share Input action of Input Capture Channels x and y
TFMOD — Timer Flag-setting Mode
Read: any time
Write: May be written once (SMODN=1). Writes are always permitted
when SMODN=0.
Use of the TFMOD bit in the ICSYS register ($AB) in conjunction with
the use of the ICOVW register ($AA) allows a timer interrupt to be
generated after capturing two values in the capture and holding
registers instead of generating an interrupt for every capture.
By setting TFMOD in queue mode, when NOVW bit is set and the
corresponding capture and holding registers are emptied, an input
capture event will first update the related input capture register with
0 = The contents of the related capture register or holding register
1 = The related capture register or holding register cannot be
0 = Normal operation
1 = The channel input ‘x’ causes the same action on the channel
SH15
5
0
can be overwritten when a new input capture or latch occurs.
written by an event unless they are empty (see
This will prevent the captured value to be overwritten until it is
read or latched in the holding register.
‘y’. The port pin ‘x’ and the corresponding edge detector is
used to be active on the channel ‘y’.
Enhanced Capture Timer
SH04
4
0
TFMOD
3
0
PACMX
2
0
BUFEN
MC68HC912D60A — Rev. 3.1
1
0
Freescale Semiconductor
LATQ
BIT 0
0
IC
Channels).
$00AB