MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 253

IC MCU 16BIT 112-LQFP

MC912D60CCPVE

Manufacturer Part Number
MC912D60CCPVE
Description
IC MCU 16BIT 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912D60CCPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
PACMX — 8-Bit Pulse Accumulators Maximum Count
BUFEN — IC Buffer Enable
LATQ — Input Control Latch or Queue Mode Enable
the main timer contents. At the next event the TCn data is transferred
to the TCnH register, The TCn is updated and the CnF interrupt flag
is set. See
In all other input capture cases the interrupt flag is set by a valid
external event on PTn.
The BUFEN control bit should be set in order to enable the IC and
pulse accumulators holding registers. Otherwise LATQ latching
modes are disabled.
Write one into ICLAT bit in MCCTL ($A6), when LATQ and BUFEN
are set will produce latching of input capture and pulse accumulators
registers into their holding registers.
0 = The timer flags C3F–C0F in TFLG1 ($8E) are set when a valid
1 = If in queue mode (BUFEN=1 and LATQ=0), the timer flags
0 = Normal operation. When the 8-bit pulse accumulator has
1 = When the 8-bit pulse accumulator has reached the value $FF,
0 = Input Capture and pulse accumulator holding registers are
1 = Input Capture and pulse accumulator holding registers are
input capture transition on the corresponding port pin occurs.
C3F–C0F in TFLG1 ($8E) are set only when a latch on the
corresponding holding register occurs.
If the queue mode is not engaged, the timer flags C3F–C0F are
set the same way as for TFMOD=0.
reached the value $FF, with the next active edge, it will be
incremented to $00.
it will not be incremented further. The value $FF indicates a
count of 255 or more.
disabled.
enabled. The latching mode is defined by LATQ control bit.
Write one into ICLAT bit in MCCTL ($A6), when LATQ is set
will produce latching of input capture and pulse accumulators
registers into their holding registers.
Enhanced Capture Timer
Figure
14-6.
Enhanced Capture Timer
Timer Registers
Technical Data
253

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