MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 268

IC MCU 16BIT 112-LQFP

MC912D60CCPVE

Manufacturer Part Number
MC912D60CCPVE
Description
IC MCU 16BIT 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912D60CCPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC912D60CCPVE
Manufacturer:
FREESCAL
Quantity:
203
Part Number:
MC912D60CCPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Multiple Serial Interface
SC0CR1/SC1CR1 — SCI Control Register 1
Technical Data
268
RESET:
LOOPS
Bit 7
0
WOMS
6
0
BTST — Reserved for test function
BSPL — Reserved for test function
BRLD — Reserved for test function
Read or write anytime.
LOOPS — SCI LOOP Mode/Single Wire Mode Enable
WOMS — Wired-Or Mode for Serial Pins
If the DDRS bit associated with the TXD pin is set during the LOOPS
= 1, the TXD pin outputs the SCI waveform. If the DDRS bit
associated with the TXD pin is clear during the LOOPS = 1, the TXD
pin becomes high (IDLE line state) for RSRC = 0 and high impedance
for RSRC = 1. Refer to
This bit controls the two pins (TXD and RXD) associated with the SCIx
section.
0 = SCI transmit and receive sections operate normally.
1 = SCI receive section is disconnected from the RXD pin and the
0 = Pins operate in a normal mode with both high and low drive
1 = Each pin operates in an open drain fashion if that pin is
RSRC
5
0
RXD pin is available as general purpose I/O. The receiver input is
determined by the RSRC bit. The transmitter output is controlled
by the associated DDRS bit. Both the transmitter and the receiver
must be enabled to use the LOOP or the single wire mode.
capability. To affect the RXD bit, that bit would have to be
configured as an output (via DDS0/2) which is the single wire
case when using the SCI. WOMS bit still affects general purpose
output on TXD and RXD pins when SCIx is not using these pins.
declared as an output.
Multiple Serial Interface
M
4
0
WAKE
Table
3
0
15-2.
ILT
2
0
MC68HC912D60A — Rev. 3.1
PE
1
0
Freescale Semiconductor
Bit 0
PT
0
$00C2/$00CA

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