MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 270

IC MCU 16BIT 112-LQFP

MC912D60CCPVE

Manufacturer Part Number
MC912D60CCPVE
Description
IC MCU 16BIT 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912D60CCPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC912D60CCPVE
Manufacturer:
FREESCAL
Quantity:
203
Part Number:
MC912D60CCPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Multiple Serial Interface
SC0CR2/SC1CR2 — SCI Control Register 2
Technical Data
270
RESET:
Bit 7
TIE
0
TCIE
6
0
PE — Parity Enable
PT — Parity Type
Read or write anytime.
TIE — Transmit Interrupt Enable
TCIE — Transmit Complete Interrupt Enable
In the long mode, the SCI circuitry does not begin counting ones in the
search for the idle line condition until a stop bit is received. Therefore,
the last byte’s stop bit and preceding “1” bits do not affect how quickly
an idle line condition can be detected.
If parity is enabled, this bit determines even or odd parity for both the
receiver and the transmitter.
0 = Parity is disabled.
1 = Parity is enabled.
0 = Even parity is selected. An even number of ones in the data
1 = Odd parity is selected. An odd number of ones in the data
0 = TDRE interrupts disabled
1 = SCI interrupt will be requested whenever the TDRE status flag
0 = TC interrupts disabled
1 = SCI interrupt will be requested whenever the TC status flag is
RIE
5
0
character causes the parity bit to be zero and an odd number
of ones causes the parity bit to be one.
character causes the parity bit to be zero and an even number
of ones causes the parity bit to be one.
is set.
set.
Multiple Serial Interface
ILIE
4
0
TE
3
0
RE
2
0
RWU
MC68HC912D60A — Rev. 3.1
1
0
Freescale Semiconductor
Bit 0
SBK
0
$00C3/$00CB

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