MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 285

IC MCU 16BIT 112-LQFP

MC912D60CCPVE

Manufacturer Part Number
MC912D60CCPVE
Description
IC MCU 16BIT 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912D60CCPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
MC912D60CCPVE
Manufacturer:
FREESCAL
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Part Number:
MC912D60CCPVE
Manufacturer:
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Quantity:
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PORTS — Port S Data Register
15.6 Port S
DDRS — Data Direction Register for Port S
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Function
RESET:
Pin
DDS7
Bit 7
Bit 7
PS7
SS
CS
0
DDS6
SCK
PS6
6
0
6
some slave devices are very simple and either accept data from the
master without returning data to the master or pass data to the master
without requiring data from the master.
In all modes, port S bits PS[7:0] can be used for either general-purpose
I/O, or with the SCI and SPI subsystems. During reset, port S pins are
configured as high-impedance inputs (DDRS is cleared).
Read anytime (inputs return pin level; outputs return pin driver input
level). Write data stored in internal latch (drives pins only if configured for
output). Writes do not change pin state when pin configured for SPI or
SCI output.
After reset all bits are configured as general-purpose inputs.
Port S shares function with the on-chip serial systems (SPI and SCI0/1).
Read or write anytime.
After reset, all general-purpose I/O are configured for input only.
0 = Configure the corresponding I/O pin for input only
1 = Configure the corresponding I/O pin for output
MOMI
DDS5
MOSI
PS5
5
5
0
Multiple Serial Interface
DDS4
MISO
SISO
PS4
4
4
0
DDS3
TXD1
PS3
3
3
0
DDS2
RXD1
PS2
2
0
2
DDS1
TXD0
PS1
1
0
1
Multiple Serial Interface
DDS0
RXD0
Bit 0
Bit 0
PS0
0
Technical Data
$00D6
$00D7
Port S
285

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