MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 299

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SC0SR1 — MI Bus Status Register 1
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
RESET:
Bit 7
—
1
—
6
1
RDRF — Receive Data Register Full Flag
1. Note that TDRE and TC will both behave in the same way as during normal SCI transmissions.
The MI Bus will still be receiving when the TC bit becomes set, hence any queued transmission
will not start until the current pull field has finished. See also
The bits in these registers are set by various conditions in the MI Bus
hardware and are automatically cleared by special acknowledge
sequences. The receive related flag bits in SC0SR1 (RDRF, OR and
NF) are all cleared by a read of this register followed by a read of the
transmit/receive data register low byte. However, only those bits
which were set when SC0SR1 was read will be cleared by the
subsequent read of the transmit/receive data register low byte.
Read anytime (used in auto clearing mechanism). Write has no
meaning or effect.
The EOF (end-of-frame) during an MI Bus pull-field is a continuous
square wave, which will result in multiple RDRFs. This may be dealt
with in any of the following ways:
0 = Contents of the receiver shift register have not been transferred
1 = Contents of the receiver serial shift register have been
– By clearing the RIE mask, ignoring unneeded RDRFs, initiating
– By clearing the RE bit when a pull field is complete, followed by
– By disabling the MI Bus.
RDRF
5
0
to the receiver data register.
transferred to the receiver data register.
a push field, waiting for TDRE
setting the RE bit after the TDRE
push field is asserted.
Freescale Interconnect Bus
—
4
0
OR
3
0
NF
2
0
(1)
1
and then clearing the RDRF
flag associated with the next
Register
—
1
0
Freescale Interconnect Bus
Descriptions.
SCI0/MI Bus registers
Bit 0
—
0
Technical Data
$00C4
299