MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 301

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SC0DRL— MI Bus Data Register Low
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Push field
Pull field
RESET:
R7/T7
Bit 7
A2
—
0
R6/T6
A1
—
6
1
RAF — Receiver Active Flag
R7T7–R0T0 — Receive/Transmit Data Bits 7 to 0
This register forms the 8-bit data/address word for the MI push field
and contains the 3-bit data word received as the MI pull field.
READ: Reads access the three bits of pull field data (stored in bits
3–1) of the read-only MI Bus receive data register. Bits [7:4, 0] are a
fixed data pattern when a valid status and end-of-frame is returned. A
valid status is represented by the following data pattern: 0101 xxx1
(bits 7–0), where ‘xxx’ is the status. All ones in the receive data
register indicate that an error occurred on the MI Bus. Bits are
received LSB first by the MCU, and the status bits map as shown in
the above table.
0 = A character is not being received
1 = A character is being received
R5/T5
A0
—
5
0
Freescale Interconnect Bus
1. 20kHz bit rate requires 25µs (40kHz) time slots.
2. 25µs ÷ 16
MDL1
R4/T4
D4
0
0
1
1
—
4
1
Table 16-1. MI Bus Delay
MDL0
R3/T3
D3
S1
—
3
0
1
0
1
Delay factor Delay time
R2/T2
D2
S2
—
2
1
2
3
4
R1/T1
S3
D1
1.5625 µs
—
1
4.6875 µs
3.125 µs
Freescale Interconnect Bus
6.25 µs
SCI0/MI Bus registers
R0/T0
(2)
Bit 0
(1)
D0
—
1
Technical Data
$00C7
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