MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 311

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
cause of the receiver interrupt. When more than one hit occurs (two or
more filters match) the lower hit has priority.
A very flexible programmable generic identifier acceptance filter has
been introduced in order to reduce the CPU interrupt loading. The filter
is programmable to operate in four different modes:
•
•
•
•
Two identifier acceptance filters, each to be applied to a) the full
29 bits of the extended identifier and to the following bits of the
CAN frame: RTR, IDE, SRR or b) the 11 bits of the standard
identifier, the RTR and IDE bits of CAN 2.0A/B messages. This
mode implements two filters for a full length CAN 2.0B compliant
extended identifier.
bank (CIDAR0–3, CIDMR0–3) produces a filter 0 hit. Similarly, the
second filter bank (CIDAR4–7, CIDMR4–7) produces a filter 1 hit.
Four identifier acceptance filters, each to be applied to a) the 14
most significant bits of the extended identifier plus the SRR and
IDE bits of CAN 2.0B messages or b) the 11 bits of the standard
identifier, the RTR and IDE bits of CAN 2.0A/B mesages.
17-4
produces filter 0 and 1 hits. Similarly, the second filter bank
(CIDAR4–7, CIDMR4–7) produces filter 2 and 3 hits.
Eight identifier acceptance filters, each to be applied to the first 8
bits of the identifier. This mode implements eight independent
filters for the first 8 bits of a CAN 2.0A/B compliant standard
identifier or of a CAN 2.0B compliant extended identifier.
17-5
produces filter 0 to 3 hits. Similarly, the second filter bank
(CIDAR4–7, CIDMR4–7) produces filter 4 to 7 hits.
Closed filter. No CAN message will be copied into the foreground
buffer RxFG, and the RXF flag will never be set.
shows how the first 32-bit filter bank (CIDAR0–3, CIDMR0–3)
shows how the first 32-bit filter bank (CIDAR0–3, CIDMR0–3)
MSCAN Controller
Figure 17-3
shows how the first 32-bit filter
Identifier Acceptance Filter
MSCAN Controller
Technical Data
Figure
Figure
311