MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 315

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.6.1 Interrupt Acknowledge
17.6.2 Interrupt Vectors
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
NOTE:
Interrupts are directly associated with one or more status flags in either
the msCAN12 receiver flag register (CRFLG) or the msCAN12
transmitter flag register (CTFLG). Interrupts are pending as long as one
of the corresponding flags is set. The flags in above registers must be
reset within the interrupt handler in order to handshake the interrupt. The
flags are reset through writing a 1 to the corresponding bit position. A flag
cannot be cleared if the respective condition still prevails.
Bit manipulation instructions (BSET) shall not be used to clear interrupt
flags.
The msCAN12 supports four interrupt vectors as shown in
The vector addresses and the relative interrupt priority are dependent on
the chip integration and to be defined.
Interrupts
Function
Wake-Up
Transmit
Receive
Error
Table 17-1. msCAN12 Interrupt Vectors
MSCAN Controller
RWRNIF
TWRNIF
RERRIF
TERRIF
BOFFIF
Source
WUPIF
OVRIF
TXE0
TXE1
TXE2
RXF
Local Mask
RWRNIE
TWRNIE
RERRIE
TERRIE
BOFFIE
TXEIE0
TXEIE1
TXEIE2
WUPIE
OVRIE
RXFIE
Global Mask
MSCAN Controller
I Bit
Table
Technical Data
Interrupts
17-1.
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