MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 316

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MSCAN Controller
17.7 Protocol Violation Protection
17.8 Low Power Modes
Technical Data
316
The msCAN12 will protect the user from accidentally violating the CAN
protocol through programming errors. The protection logic implements
the following features:
In addition to normal mode, the msCAN12 has three modes with
reduced power consumption: SLEEP, SOFT_RESET and
POWER_DOWN mode. In SLEEP and SOFT_RESET modes, power
consumption is reduced by stopping all clocks except those to access
the registers. In POWER_DOWN mode, all clocks are stopped and no
power is consumed.
The WAI and STOP instructions put the MCU in low power consumption
stand-by modes.
and CPU modes. A particular combination of modes is entered for the
given settings of the bits CSWAI, SLPAK, and SFTRES. For all modes,
an msCAN wake-up interrupt can occur only if SLPAK=WUPIE=1. While
the CPU is in Wait Mode, the msCAN12 can be operated in Normal
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•
•
The receive and transmit error counters cannot be written or
otherwise manipulated.
All registers which control the configuration of the msCAN12
cannot be modified while the msCAN12 is on-line. The SFTRES
bit in CMCR0 (see
(CMCR0)) serves as a lock to protect the following registers:
– msCAN12 module control register 1 (CMCR1)
– msCAN12 bus timing register 0 and 1 (CBTR0, CBTR1)
– msCAN12 identifier acceptance control register (CIDAC)
– msCAN12 identifier acceptance registers (CIDAR0–7)
– msCAN12 identifier mask registers (CIDMR0–7)
The TxCAN pin is forced to recessive when the msCAN12 is in any
of the low power modes.
MSCAN Controller
Table 17-2
msCAN12 Module Control Register 0
summarizes the combinations of msCAN12
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor