MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 320

IC MCU 16BIT 112-LQFP

MC912D60CCPVE

Manufacturer Part Number
MC912D60CCPVE
Description
IC MCU 16BIT 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912D60CCPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number:
MC912D60CCPVE
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MSCAN Controller
17.8.3 msCAN12 POWER_DOWN Mode
17.8.4 Programmable Wake-Up Function
17.9 Timer Link
Technical Data
320
NOTE:
The msCAN12 is in POWER_DOWN mode when
When entering the POWER_DOWN mode, the msCAN12 immediately
stops all ongoing transmissions and receptions, potentially causing CAN
protocol violations.
The user is responsible for ensuring that the msCAN12 is not active
when POWER_DOWN mode is entered. The recommended procedure
is to bring the msCAN12 into SLEEP mode before the STOP instruction
(or the WAI instruction, if CSWAI is set) is executed.
To protect the CAN bus system from fatal consequences of violations to
the above rule, the msCAN12 drives the TxCAN pin into recessive state.
In POWER_DOWN mode no registers can be accessed.
The msCAN12 can be programmed to apply a low-pass filter function to
the RxCAN input line while in SLEEP mode (see control bit WUPM in the
module control register,
(CMCR1).). This feature can be used to protect the msCAN12 from
wake-up due to short glitches on the CAN bus lines. Such glitches can
result from electromagnetic interference within noisy environments.
The msCAN12 generates a timer signal whenever a valid frame has
been received. Because the CAN specification defines a frame to be
valid if no errors occurred before the EOF field has been transmitted
successfully, the timer signal is generated right after the EOF. A pulse of
one bit time is generated. As the msCAN12 receiver engine also
the CPU is in STOP mode or
the CPU is in WAIT mode and the CSWAI bit is set (see
Module Control Register 0
MSCAN Controller
msCAN12 Module Control Register 1
(CMCR0)).
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
msCAN12

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