MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 329

IC MCU 16BIT 112-LQFP

MC912D60CCPVE

Manufacturer Part Number
MC912D60CCPVE
Description
IC MCU 16BIT 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912D60CCPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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17.12.4 Data Segment Registers (DSRn)
17.12.5 Transmit Buffer Priority Registers (TBPR)
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
1. x is 5, 6, or 7 depending on which buffer Tx0, Tx1, or Tx2 respectively.
TBPR
$01xD
RESET
(1)
R
W
PRIO7
BIT 7
The eight data segment registers contain the data to be transmitted or
being received. The number of bytes to be transmitted or being received
is determined by the data length code in the corresponding DLR.
PRIO7 – PRIO0 — Local Priority
PRIO6
BIT 6
This field defines the local priority of the associated message buffer.
The local priority is used for the internal prioritisation process of the
msCAN12 and is defined to be highest for the smallest binary number.
The msCAN12 implements the following internal prioritisation
mechanism:
All transmission buffers with a cleared TXE flag participate in the
prioritisation immediately before the SOF (Start of Frame) is sent.
The transmission buffer with the lowest local priority field wins the
prioritisation.
In cases of more than one buffer having the same lowest priority,
the message buffer with the lower index number wins.
PRIO5
BIT 5
MSCAN Controller
PRIO4
BIT 4
PRIO3
BIT 3
Programmer’s Model of Message Storage
PRIO2
BIT 2
PRIO1
BIT 1
MSCAN Controller
Technical Data
PRIO0
BIT 0
329

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