MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 332

IC MCU 16BIT 112-LQFP

MC912D60CCPVE

Manufacturer Part Number
MC912D60CCPVE
Description
IC MCU 16BIT 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912D60CCPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Manufacturer
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Price
Part Number:
MC912D60CCPVE
Manufacturer:
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MC912D60CCPVE
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MSCAN Controller
17.13.3 msCAN12 Module Control Register 1 (CMCR1).
Technical Data
332
CMCR1
$0101
RESET
W
R
NOTE:
Bit 7
0
0
LOOPB — Loop Back Self Test Mode
WUPM — Wake-Up Mode
CLKSRC — msCAN12 Clock Source
The CMCR1 register can be written only if the SFTRES bit in CMCR0 is
set.
When this bit is set the msCAN12 performs an internal loop back
which can be used for self test operation: the bit stream output of the
transmitter is fed back to the receiver internally. The RxCAN input pin
is ignored and the TxCAN output goes to the recessive state (1). The
msCAN12 behaves as it does normally when transmitting and treats
its own transmitted message as a message received from a remote
node. In this state the msCAN12 ignores the bit sent during the ACK
slot of the CAN frame acknowledge field to insure proper reception of
its own message. Both transmit and receive interrupts are generated.
This flag defines whether the integrated low-pass filter is applied to
protect the msCAN12 from spurious wake-ups (see
Wake-Up
This flag defines which clock source the msCAN12 module is driven from
(only for system with CGM module; see
6
0
0
0 = Normal operation
1 = Activate loop back self test mode
0 = msCAN12 will wake up the CPU after any recessive to
1 = msCAN12 will wake up the CPU only in the case of dominant pulse
0 = The msCAN12 clock source is EXTALi.
1 = The msCAN12 clock source is SYSCLK, twice the frequency of
dominant edge on the CAN bus.
on the bus which has a length of at least approximately T
ECLK.
Function).
5
0
0
MSCAN Controller
4
0
0
3
0
0
Clock
LOOPB
2
0
MC68HC912D60A — Rev. 3.1
System,
Freescale Semiconductor
WUPM
Programmable
1
0
Figure
17-7).
CLKSRC
wup
Bit 0
0
.

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