MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 333

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.13.4 msCAN12 Bus Timing Register 0 (CBTR0)
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
CBTR0
$0102
RESET
R
W
NOTE:
SJW1
Bit 7
0
SJW1, SJW0 — Synchronization Jump Width
BRP5 – BRP0 — Baud Rate Prescaler
The CBTR0 register can only be written if the SFTRES bit in CMCR0 is
set.
SJW0
The synchronization jump width defines the maximum number of time
quanta (Tq) clock cycles by which a bit may be shortened, or
lengthened, to achieve resynchronization on data transitions on the
bus (see
These bits determine the time quanta (Tq) clock, which is used to
build up the individual bit timing, according to
6
0
BRP5
0
0
0
0
1
:
:
SJW1
0
0
1
1
Table
BRP5
BRP4
5
0
Table 17-5. Synchronization jump width
0
0
0
0
1
:
:
MSCAN Controller
17-5).
Table 17-6. Baud rate prescaler
BRP3
BRP4
0
0
0
0
1
:
:
4
0
SJW0
0
1
0
1
BRP2
0
0
0
0
1
:
:
BRP3
3
0
Programmer’s Model of Control Registers
BRP1
0
0
1
1
1
:
:
Synchronization jump width
BRP2
2
0
BRP0
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
1 Tq clock cycle
0
1
0
1
1
:
:
Table
Prescaler value
BRP1
17-6.
1
0
MSCAN Controller
Technical Data
(P)
64
1
2
3
4
:
:
BRP0
Bit 0
0
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