MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 334

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MSCAN Controller
17.13.5 msCAN12 Bus Timing Register 1 (CBTR1).
Technical Data
334
CBTR1
$0103
RESET
R
W
SAMP
Bit 7
0
SAMP — Sampling
TSEG22 – TSEG10 — Time Segment
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are
programmable as shown in
1. In this case, PHASE_SEG1 must be at least two time quanta.
TSEG22
This bit determines the number of samples of the serial bus to be
taken per bit time. If set three samples per bit are taken, the regular
one (sample point) and two preceding samples, using a majority rule.
For higher bit rates SAMP should be cleared, which means that only
one sample will be taken per bit.
Time segments within the bit time fix the number of clock cycles per
bit time, and the location of the sample point. (See
6
0
0 = One sample per bit.
1 = Three samples per bit.
TSEG21
Transmit point
Sample point
SYNC_SEG
5
0
MSCAN Controller
Table 17-7. Time segment syntax
TSEG20
4
0
A node in transmit mode will transfer a new
A node in receive mode will sample the bus
option is selected then this point marks the
System expects transitions to occur on the
at this point. If the three samples per bit
Table
value to the CAN bus at this point.
(1)
TSEG13
position of the third sample.
17-8.
bus during this period.
3
0
TSEG12
2
0
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
TSEG11
Figure
1
0
17-8)
TSEG10
Bit 0
0