MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 345

IC MCU 16BIT 112-LQFP

MC912D60CCPVE

Manufacturer Part Number
MC912D60CCPVE
Description
IC MCU 16BIT 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912D60CCPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC912D60CCPVE
Manufacturer:
FREESCAL
Quantity:
203
Part Number:
MC912D60CCPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
17.13.14 msCAN12 Identifier Mask Registers (CIDMR0–7)
CIDMR4
$011C
CIDMR5
$011D
CIDMR6
$011E
CIDMR7
$011F
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
CIDMR0
$0114
CIDMR1
$0115
CIDMR2
$0116
CIDMR3
$0117
RESET
RESET
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
AM7
AM7
AM7
AM7
Bit 7
AM7
AM7
AM7
AM7
Bit 7
The identifier mask register specifies which of the corresponding bits in
the identifier acceptance register are relevant for acceptance filtering. To
receive standard identifiers in 32 bit filter mode it is required to program
the last three bits (AM2–AM0) in the mask registers CIDMR1 and
CIDMR5 to ‘don’t care’. To receive standard identifiers in 16 bit filter
mode it is required to program the last three bits (AM2–AM0) in the mask
registers CIDMR1, CIDMR3, CIDMR5 and CIDMR7 to ‘don’t care’.
AM6
AM6
AM6
AM6
AM6
AM6
AM6
AM6
6
6
AM5
AM5
AM5
AM5
AM5
AM5
AM5
AM5
5
5
MSCAN Controller
AM4
AM4
AM4
AM4
AM4
AM4
AM4
AM4
4
4
AM3
AM3
AM3
AM3
AM3
AM3
AM3
AM3
3
3
Programmer’s Model of Control Registers
AM2
AM2
AM2
AM2
AM2
AM2
AM2
AM2
2
2
AM1
AM1
AM1
AM1
AM1
AM1
AM1
AM1
1
1
MSCAN Controller
Technical Data
AM0
AM0
AM0
AM0
AM0
AM0
AM0
AM0
Bit 0
Bit 0
345

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