MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 346

IC MCU 16BIT 112-LQFP

MC912D60CCPVE

Manufacturer Part Number
MC912D60CCPVE
Description
IC MCU 16BIT 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912D60CCPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC912D60CCPVE
Manufacturer:
FREESCAL
Quantity:
203
Part Number:
MC912D60CCPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MSCAN Controller
17.13.15 msCAN12 Port CAN Control Register (PCTLCAN)
Technical Data
346
PCTLCAN
$013D
RESET
R
W
NOTE:
Bit 7
0
0
AM7 – AM0 — Acceptance Mask Bits
The CIDMR0–7 registers can only be written if the SFTRES bit in
CMCR0 is set.
The following bits control pins 7 through 2 of Port CAN. Pins 1 and 0 are
reserved for the RxCan (input only) and TxCan (output only) pins.
PUPCAN — Pull-Up Enable Port CAN
In 80QFP all PortCAN[2:7] pins should either be defined as outputs or
have their pull-ups enabled.
RDPCAN — Reduced Drive Port CAN
If a particular bit in this register is cleared this indicates that the
corresponding bit in the identifier acceptance register must be the same
as its identifier bit, before a match is detected. The messageis accepted
if all such bits match. If a bit is set, it indicates that the state of the
corresponding bit in the identifier acceptance register does not affect
whether or not the message is accepted.
Bit description:
6
0
0
0 = Match corresponding acceptance code register and identifier
1 = Ignore corresponding acceptance code register bit.
0 = Pull mode disabled for Port CAN.
1 = Pull mode enabled for Port CAN.
0 = Reduced drive disabled for Port CAN.
1 = Reduced drive enabled for Port CAN.
bits.
5
0
0
MSCAN Controller
4
0
0
3
0
0
2
0
0
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
PUPCAN
1
0
RDPCAN
Bit 0
0

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