MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 35

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.6 Indexed Addressing Modes
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
rr0nnnnn
111rr0zs
111rr011
rr1pnnnn
111rr1aa
111rr111
Code (xb)
Postbyte
The CPU12 indexed modes reduce execution time and eliminate code
size penalties for using the Y index register. CPU12 indexed addressing
uses a postbyte plus zero, one, or two extension bytes after the
instruction opcode. The postbyte and extensions do the following tasks:
,r
n,r
[n,r]
n,–r n,+r
A,r
[D,r]
•
•
•
•
n,r
–n,r
–n,r
n,r– n,r+
B,r
D,r
Source
Syntax
Code
Specify which index register is used.
Determine whether a value in an accumulator is used as an offset.
Enable automatic pre- or post-increment or decrement
Specify use of 5-bit, 9-bit, or 16-bit signed offsets.
Table 2-2. Summary of Indexed Operations
5-bit constant offset n = –16 to +15
Constant offset (9- or 16-bit signed)
16-bit offset indexed-indirect
Auto pre-decrement/increment or Auto post-
Accumulator offset (unsigned 8-bit or 16-bit)
Accumulator D offset indexed-indirect
Central Processing Unit
rr can specify X, Y, SP, or PC
z-0 = 9-bit with sign in LSB of postbyte(s)
1 = 16-bit
if z = s = 1, 16-bit offset indexed-indirect (see below)
rr can specify X, Y, SP, or PC
rr can specify X, Y, SP, or PC
decrement/increment;
p = pre-(0) or post-(1), n = –8 to –1, +1 to +8
rr can specify X, Y, or SP (PC not a valid choice)
aa-00 = A
01 = B
10 = D (16-bit)
11 = see accumulator D offset indexed-indirect
rr can specify X, Y, SP, or PC
rr can specify X, Y, SP, or PC
Comments
Indexed Addressing Modes
Central Processing Unit
Technical Data
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