MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 382

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Development Support
Technical Data
382
SPEEDUP PULSE
START OF BIT TIME
BKGD PIN
BKGD PIN
DRIVE TO
(TARGET
BDMCLK
TARGET MCU
HOST
DRIVE AND
MCU)
PERCEIVED
Figure 19-3. BDM Target to Host Serial Bit Timing (Logic 0)
Figure 19-2
MC68HC912D60A MCU. Since the host is asynchronous to the target
MCU, there is a 0-to-1 cycle delay from the host-generated falling edge
on BKGD to the perceived start of the bit time in the target MCU. The
host holds the BKGD pin low long enough for the target to recognize it
(at least two target B cycles). The host must release the low drive before
the target MCU drives a brief active-high speed-up pulse seven cycles
after the perceived start of the bit time. The host should sample the bit
level about ten cycles after it started the bit time.
Figure 19-3
MC68HC912D60A MCU. Since the host is asynchronous to the target
MCU, there is a 0-to-1 cycle delay from the host-generated falling edge
on BKGD to the start of the bit time as perceived by the target MCU. The
host initiates the bit time but the target MC68HC912D60A finishes it.
Since the target wants the host to receive a logic zero, it drives the
BKGD pin low for 13 BDMCLK cycles, then briefly drives it high to speed
up the rising edge. The host samples the bit level about ten cycles after
starting the bit time.
10 CYCLES
shows the host receiving a logic one from the target
shows the host receiving a logic zero from the target
Development Support
10 CYCLES
HIGH-IMPEDANCE
HOST SAMPLES
BKGD PIN
SPEEDUP PULSE
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
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