MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 387

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.4.4.2 Disabling BDM lockout
19.4.5 BDM Registers
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
NOTE:
Disabling the BDM lockout is only possible in special modes
(SMODN=0) except in special single chip mode. Follow the same steps
as for enabling the BDM lockout, but erase the SHADOW byte.
At the next reset, the SHADOW byte is loaded into the EEMCR register.
NOBDML bit in EEMCR will be set and BDM becomes operational.
When the BDM lockout is enabled it is not possible to run code from the
reset vector in special single chip mode.
Seven BDM registers are mapped into the standard 64-Kbyte address
space when BDM is active. Mapping is shown in
4. Protect the SHADOW byte by setting SHPROT bit in EEPROT
•
•
•
program other bits of the SHADOW byte (location $0FC0);
otherwise some regular EEPROM array locations will not be
visible. At the next reset, the SHADOW byte is loaded into the
EEMCR register. NOBDML bit in EEMCR will be cleared and BDM
will not be operational.
register.
The INSTRUCTION register content is determined by the type of
background command being executed.
The STATUS register indicates BDM operating conditions.
The SHIFT register contains data being received or transmitted
via the serial interface.
$FF02 - $FF03
$FF04 - $FF05
Development Support
Address
$FF00
$FF01
$FF06
Table 19-4. BDM registers
BDM CCR Holding Register
BDM Instruction Register
BDM Address Register
BDM Status Register
BDM Shift Register
Register
Table
Background Debug Mode
Development Support
19-4.
Technical Data
387