MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 400

IC MCU 16BIT 112-LQFP

MC912D60CCPVE

Manufacturer Part Number
MC912D60CCPVE
Description
IC MCU 16BIT 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912D60CCPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC912D60CCPVE
Manufacturer:
FREESCAL
Quantity:
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Part Number:
MC912D60CCPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Development Support
Technical Data
400
BKMBL — Breakpoint Mask Low
BK1RWE — R/W Compare Enable
BK1RW — R/W Compare Value
BK0RWE — R/W Compare Enable
BK0RW — R/W Compare Value
Disables the matching of the low byte of data when in full breakpoint
mode. Used in conjunction with the BKDBE bit (which should be set)
Enables the comparison of the R/W signal to further specify what
causes a match. This bit is NOT useful in program breakpoints or in
full breakpoint mode. This bit is used in conjunction with a second
address in dual address mode when BKDBE=1.
When BK1RWE = 1, this bit determines the type of bus cycle to
match.
Enables the comparison of the R/W signal to further specify what
causes a match. This bit is not useful in program breakpoints.
When BK0RWE = 1, this bit determines the type of bus cycle to match
on.
0 = Low byte of data bus (bits 7:0) are compared to BRKDL
1 = Low byte is not used in comparisons.
0 = R/W is not used in comparisons
1 = R/W is used in comparisons
0 = A write cycle will be matched
1 = A read cycle will be matched
0 = R/W is not used in the comparisons
1 = R/W is used in comparisons
0 = Write cycle will be matched
1 = Read cycle will be matched
Development Support
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor

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