MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 49

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.5.9 Read/Write (R/W)
3.5.10 Low-Byte Strobe (LSTRB)
3.5.11 Instruction Queue Tracking Signals (IPIPE1 and IPIPE0)
3.5.12 Data Bus Enable (DBE)
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
In all modes this pin can be used as general-purpose I/O and is an input
with an active pull-up out of reset. If the read/write function is required it
should be enabled by setting the RDWE bit in the PEAR register.
External writes will not be possible until enabled.
In all modes this pin can be used as general-purpose I/O and is an input
with an active pull-up out of reset. If the strobe function is required, it
should be enabled by setting the LSTRE bit in the PEAR register. This
signal is used in write operations and so external low byte writes will not
be possible until this function is enabled. This pin is also used as TAGLO
in Special Expanded modes and is multiplexed with the LSTRB function.
These signals are used to track the state of the internal instruction
execution queue. Execution state is time-multiplexed on the two signals.
Refer to
The DBE pin (PE7) is an active low signal that will be asserted low during
ECLK high time. DBE provides separation between output of a
multiplexed address and the input of data. When an external address is
stretched, DBE is asserted during what would be the last quarter cycle
of the last ECLK cycle of stretch. In expanded modes this pin is used to
enable the drive control of external buses during external reads. Use of
the DBE is controlled by the NDBE bit in the PEAR register.DBE is
enabled out of reset in expanded modes. This pin has an active pull-up
during and after reset in single chip modes.
Development
Pinout and Signal Descriptions
Support.
Pinout and Signal Descriptions
Signal Descriptions
Technical Data
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