MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 56

IC MCU 16BIT 112-LQFP

MC912D60CCPVE

Manufacturer Part Number
MC912D60CCPVE
Description
IC MCU 16BIT 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912D60CCPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC912D60CCPVE
Manufacturer:
FREESCAL
Quantity:
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Part Number:
MC912D60CCPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Pinout and Signal Descriptions
3.6.6 Port CAN
3.6.7 Port AD1
Technical Data
56
configured for output. On reset the DDRH bits are cleared and the
corresponding pin is configured for input.
Port PHUPD determines what type of resistive load is used for Port H
input pins when PUPH bit is set in the PUCR register. When PHUPD pin
is low, it loads a pull-down in all Port H input pins. When PHUPD pin is
high, it loads a pull-up in all Port H input pins.
In 80-pin version, the PHUPD is connected internally to VSS. The PH4
will have a pull-down. All port H pins should either be defined as outputs
or have their pull-downs enabled.
Setting the RDPH bit in register RDRIV causes all Port H outputs to have
reduced drive level. RDRIV can be written once after reset. RDRIV is not
in the address map in peripheral mode. Refer to
Input/Output.
The MSCAN12 uses two external pins, one input (RxCAN) and one
output (TxCAN). The TxCAN output pin represents the logic level on the
CAN: ‘0’ is for a dominant state, and ‘1’ is for a recessive state. If the
MSCAN is not used, TxCAN should be left unconnected and, due to an
internal pull-up, the RxCAN pin should not be tied to VSS.
RxCAN is on bit 0 of Port CAN, TxCAN is on bit 1. The remaining six pins
of Port CAN, available only in the 112-pin package, are controlled by
registers in the MSCAN12 address space.
In 80QFP all PortCAN[2:7] pins should either be defined as outputs or
have their pull-ups enabled.
Input to the analog-to-digital subsystem and general-purpose input.
When analog-to-digital functions are not enabled, the port has eight
general-purpose input pins, PAD1[7:0]. The ADPU bit in the ATD1CTL2
register enables the A/D function.
Pinout and Signal Descriptions
MC68HC912D60A — Rev. 3.1
Bus Control and
Freescale Semiconductor

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