D12674RVFQ33 Renesas Electronics America, D12674RVFQ33 Datasheet - Page 219

• Manufacturer Part Number: D12674RVFQ33
• Description: IC H8S MCU ROMLESS 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33; HD6412674RVFQ33

2.2.57 (6)
SHAL (SHift Arithmetic Left)
Operation
ERd (left arithmetic shift)
Assembly-Language Format
SHAL.L #2, ERd
Operand Size
Longword
Description
This instruction shifts the bits in a 32-bit register ERd (destination operand) two bits to the left.
Bit 30 shifts into the carry flag. Bits 0 and 1 are cleared to 0.
Available Registers
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Notes
The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag.
Register direct
Addressing
Mode
SHAL (L)
Mnemonic
SHAL.L
C
ERd
MSB
Operands
b31
#2, ERd
b30
. . . . . .
1st byte
1
0
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Receives the previous value in bit 30.
2nd byte
F
Instruction Format
cleared to 0.
cleared to 0.
cleared to 0.
Rev. 4.00 Feb 24, 2006 page 203 of 322
—
I
0 erd
UI H
—
b1
0
Section 2 Instruction Descriptions
—
3rd byte
LSB
b0
0
—
U
N
0
4th byte
REJ09B0139-0400
Shift Arithmetic
Z
V
States
No. of
C
1