D12674RVFQ33 Renesas Electronics America, D12674RVFQ33 Datasheet - Page 324
D12674RVFQ33
Manufacturer Part Number
D12674RVFQ33
Description
IC H8S MCU ROMLESS 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of D12674RVFQ33
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33
HD6412674RVFQ33
HD6412674RVFQ33
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
D12674RVFQ33V
Manufacturer:
VISHAY
Quantity:
2 696
Company:
Part Number:
D12674RVFQ33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 2 Instruction Descriptions
Instruction
SHAR
SHLL
SHLR
SLEEP
STC
STM
STMAC
SUB
SUBS
SUBX
TAS
TRAPA
XOR
XORC
Note: * These instructions are supported by the H8S/2600 CPU only.
Rev. 4.00 Feb 24, 2006 page 308 of 322
REJ09B0139-0400
*
H
—
—
— 0
— — —
— — —
— — —
—
— — —
—
— — —
—
N
Z
V
0
0
0
— —
— —
— —
— —
0
— —
0
C
—
—
—
Definition
N = Rm
Z = Rm · Rm–1 · ...... · R0
C = D0 (1-bit shift) or C = D1 (2-bit shift)
N = Rm
Z = Rm · Rm–1 · ...... · R0
C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)
N = Rm
Z = Rm · Rm–1 · ...... · R0
C = D0 (1-bit shift) or C = D1 (2-bit shift)
N = 1 if MAC instruction resulted in negative value in MAC register
Z = 1 if MAC instruction resulted in zero value in MAC register
V = 1 if MAC instruction resulted in overflow
H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4
N = Rm
Z = Rm · Rm–1 · ...... · R0
V = Sm · Dm · Rm + Sm · Dm · Rm
C = Sm · Dm + Dm · Rm + Sm · Rm
H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4
N = Rm
Z = Z' · Rm · ...... · R0
V = Sm · Dm · Rm + Sm · Dm · Rm
C = Sm · Dm + Dm · Rm + Sm · Rm
N = Dm
Z = Dm · Dm–1 · ...... · D0
N = Rm
Z = Rm · Rm–1 · ...... · R0
Stores the corresponding bits of the result.
No flags change when the operand is EXR.
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