R5F61622N50FPV Renesas Electronics America, R5F61622N50FPV Datasheet - Page 415
R5F61622N50FPV
Manufacturer Part Number
R5F61622N50FPV
Description
MCU 24KB FLASH 256K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61622N50FPV
Core Size
16/32-Bit
Program Memory Size
256KB (256K x 8)
Core Processor
H8SX
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b, 6x16b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
No. Of I/o's
74
Ram Memory Size
24KB
Cpu Speed
50MHz
No. Of Timers
2
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61622N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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11.1.1
DDR is an 8-bit write-only register that specifies the port input or output for each bit. A read from
the DDR is invalid and DDR is always read as an undefined value.
When the general I/O port function is selected, the corresponding pin functions as an output port
by setting the corresponding DDR bit to 1; the corresponding pin functions as an input port by
clearing the corresponding DDR bit to 0.
The initial DDR values are shown in table 11.3.
Table 11.3 Startup Mode and Initial Value
Port
Port A
Other ports
Bit
Bit Name
Initial Value
R/W
Note: The lower six bits are valid and the upper two bits are reserved for port 6 registers.
The lower five bits are valid and the upper three bits are reserved for port F registers.
Data Direction Register (PnDDR) (n = 1 to 3, 6, A, D to F, H, and I)
Pn7DDR
W
7
0
Pn6DDR
W
6
0
External Extended Mode
H'80
Pn5DDR
W
5
0
Pn4DDR
W
4
0
Pn3DDR
W
3
0
Startup Mode
Rev. 2.00 Sep. 16, 2009 Page 385 of 1036
H'00
Single-Chip Mode
H'00
Pn2DDR
W
2
0
Pn1DDR
Section 11 I/O Ports
W
1
0
REJ09B0414-0200
Pn0DDR
W
0
0
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