R5F61622N50FPV Renesas Electronics America, R5F61622N50FPV Datasheet - Page 775

• Manufacturer Part Number: R5F61622N50FPV
• Description: MCU 24KB FLASH 256K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61622N50FPV

• Core Size: 16/32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: H8SX
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b, 6x16b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• No. Of I/o's: 74
• Ram Memory Size: 24KB
• Cpu Speed: 50MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

19.3.1
DSADMR controls the biasing circuit and selects a clock for the ∆Σ A/D converter. DSADMR
can be read by the CPU at any time, but must be written to while the ∆Σ A/D converter is in the
module stop state.
[Legend]
Bit
7
6 to 3
2
1
0
Bit
Bit Name
Initial Value:
R/W:
Bit Name
BIASE

ACK2
ACK1
ACK0
∆Σ A/D Mode Register (DSADMR)
x: Don't care.
BIASE
R/W
7
0
Initial
Value
0
All 0
0
0
0

R
6
0
R/W
R/W
R
R/W
R/W
R/W

R
5
0
Description
Biasing Circuit Control
Controls whether the biasing circuit is stopped or runs.
0: Biasing circuit is stopped.
1: Biasing circuit runs.
Reserved
These bits are always read as 0. The write value should
always be 0.
∆Σ A/D Converter Clock Select
These bits select the frequency of the ∆Σ A/D converter
clock (Aφ). The values shown below for each setting are
frequency multipliers for the input clock. Set these bits so
that Aφ is approximately 25 MHz. See section 23, Clock
Pulse Generator, for details.
000: × 1/6
001: × 1/5
010: × 1/4
011: × 1/3
1xx: Setting prohibited

R
4
0

R
3
0
Rev. 2.00 Sep. 16, 2009 Page 745 of 1036
ACK2
R/W
2
0
Section 19 ∆Σ A/D Converter
ACK1
R/W
1
0
REJ09B0414-0200
ACK0
R/W
0
0