R5F61622N50FPV Renesas Electronics America, R5F61622N50FPV Datasheet - Page 84

• Manufacturer Part Number: R5F61622N50FPV
• Description: MCU 24KB FLASH 256K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61622N50FPV

• Core Size: 16/32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: H8SX
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b, 6x16b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• No. Of I/o's: 74
• Ram Memory Size: 24KB
• Cpu Speed: 50MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 2 CPU
Table 2.9
Rev. 2.00 Sep. 16, 2009 Page 54 of 1036
REJ09B0414-0200
Instruction
BSET
BSET/cc
BCLR
BCLR/cc
BNOT
BTST
BAND
BIAND
BOR
Bit Manipulation Instructions
Size
B
B
B
B
B
B
B
B
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in the contents of a general register or a memory
location to 1. The bit number is specified by 3-bit immediate data or the
lower three bits of a general register.
if cc, 1 → (<bit-No.> of <EAd>)
If the specified condition is satisfied, this instruction sets a specified bit in
a memory location to 1. The bit number can be specified by 3-bit
immediate data, or by the lower three bits of a general register. The Z flag
status can be specified as a condition.
0 → (<bit-No.> of <EAd>)
Clears a specified bit in the contents of a general register or a memory
location to 0. The bit number is specified by 3-bit immediate data or the
lower three bits of a general register.
If the specified condition is satisfied, this instruction clears a specified bit
in a memory location to 0. The bit number can be specified by 3-bit
immediate data, or by the lower three bits of a general register. The Z flag
status can be specified as a condition.
∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in the contents of a general register or a memory
location. The bit number is specified by 3-bit immediate data or the lower
three bits of a general register.
∼ (<bit-No.> of <EAd>) → Z
Tests a specified bit in the contents of a general register or a memory
location and sets or clears the Z flag accordingly. The bit number is
specified by 3-bit immediate data or the lower three bits of a general
register.
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in the contents of a general
register or a memory location and stores the result in the carry flag. The
bit number is specified by 3-bit immediate data.
C ∧ [∼ (<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in the contents of a
general register or a memory location and stores the result in the carry
flag. The bit number is specified by 3-bit immediate data.
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in the contents of a general register
or a memory location and stores the result in the carry flag. The bit
number is specified by 3-bit immediate data.
Function
if cc, 0 → (<bit-No.> of <EAd>)