MC68HC711E9VFNE2 Freescale Semiconductor, MC68HC711E9VFNE2 Datasheet - Page 183
MC68HC711E9VFNE2
Manufacturer Part Number
MC68HC711E9VFNE2
Description
IC MCU 8BIT 512BYTES ROM 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Specifications of MC68HC711E9VFNE2
Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
12KB (12K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
52-PLCC
Processor Series
HC711E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC711E9VFNE2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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9.4.1 Timer Control Register 2
M68HC11E Family — Rev. 3.2
MOTOROLA
Address:
to result in input captures. Writing to TI4/O5 has no effect when the
TI4/O5 register is acting as IC4.
Use the control bits of this register to program input capture functions to
detect a particular edge polarity on the corresponding timer input pin.
Each of the input capture functions can be independently configured to
detect rising edges only, falling edges only, any edge (rising or falling),
or to disable the input capture function. The input capture functions
operate independently of each other and can capture the same TCNT
value if the input edges are detected within the same timer count cycle.
EDGxB and EDGxA — Input Capture Edge Control Bits
Reset:
Read:
Write:
There are four pairs of these bits. Each pair is cleared to 0 by reset
and must be encoded to configure the corresponding input capture
edge detector circuit. IC4 functions only if the I4/O5 bit in the PACTL
register is set. Refer to
EDG4B
$1021
Bit 7
0
Figure 9-3. Timer Control Register 2 (TCTL2)
EDGxB
Table 9-2. Timer Control Configuration
EDG4A
0
0
1
1
Timing System
6
0
EDG1B
EDGxA
5
0
Table 9-2
0
1
0
1
EDG1A
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge
4
0
for timer control configuration.
EDG2B
Configuration
3
0
EDG2A
2
0
EDG3B
1
0
Timing System
Technical Data
Input Capture
EDG3A
Bit 0
0
183
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