MC68HC711E9VFNE2 Freescale Semiconductor, MC68HC711E9VFNE2 Datasheet - Page 85
MC68HC711E9VFNE2
Manufacturer Part Number
MC68HC711E9VFNE2
Description
IC MCU 8BIT 512BYTES ROM 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Specifications of MC68HC711E9VFNE2
Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
12KB (12K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
52-PLCC
Processor Series
HC711E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC711E9VFNE2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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4.4.3 System Initialization
M68HC11E Family — Rev. 3.2
MOTOROLA
SMOD = 0
SMOD = 1
Operating
Mode
Register
Address
$x03C
$x03D
$x03C
$x03D
$x024
$x035
$x039
$x024
$x035
$x039
Registers and bits that control initialization and the basic operation of the
MCU are protected against writes except under special circumstances.
Table 4-2
must be written within the first 64 cycles after reset.
Timer interrupt mask 2 (TMSK2)
Block protect register (BPROT)
System configuration
Highest priority I-bit interrupt
System configuration options
Highest priority I-bit interrupt and
RAM and I/O map register (INIT)
Timer interrupt mask 2 (TMSK2)
Block protect register (BPROT)
RAM and I/O map register (INIT)
Table 4-2. Write Access Limited Registers
options (OPTION)
and miscellaneous (HPRIO)
(OPTION)
miscellaneous (HPRIO)
Operating Modes and On-Chip Memory
Register Name
lists registers that can be written only once after reset or that
Bits [1:0], once only
Clear bits, once only
Bits [5:4], bits [2:0],
See HPRIO
Yes, once only
See HPRIO
once only
description
description
in First 64 Cycles
Must be Written
Operating Modes and On-Chip Memory
—
—
—
—
Bits [7:2]
Set bits only
Bits [7:6], bit 3
See HPRIO
All, set or clear
All, set or clear
All, set or clear
See HPRIO
All, set or clear
description
description
Technical Data
Anytime
Memory Map
Write
—
85
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