R5F64175DFD#U0 Renesas Electronics America, R5F64175DFD#U0 Datasheet - Page 180

• Manufacturer Part Number: R5F64175DFD#U0
• Description: MCU 384+8KB FLASH 40K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C/R32C/100/117r

Specifications of R5F64175DFD#U0

• Core Processor: R32C/100
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 120
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R32C/117 Group
REJ09B0533-0110
Sep 08, 2010
11.13 Intelligent I/O Interrupt
Figure 11.12 Intelligent I/O Interrupt Block Diagram (i = 0 to 11)
Interrupt request
Interrupt request
Interrupt request
The intelligent I/O interrupt is assigned to software interrupt numbers from 44 to 55.
Figure 11.12 shows a block diagram of the intelligent I/O interrupt. Figure 11.13 and Figure 11.14 show
registers IIOiIR and IIOiIE (i = 0 to 11), respectively.
To use the intelligent I/O interrupt, the IRLT bit in the IIOiIE register should be set to 1 (interrupt requests
used for interrupt).
The intelligent I/O interrupt contains various request sources. When an interrupt request is generated with
an intelligent I/O function, the corresponding bit in the IIOiIR register becomes 1 (interrupts requested). If
the corresponding bit in the IIOiIE register is set to 1 (interrupt enabled), the IR bit in the corresponding
IIOiIC register changes to 1 (interrupts requested).
After the IR bit setting changes from 0 to 1, this bit remains unchanged if a bit in the IIOiIR register is set
to 1 by another interrupt request source and the corresponding bit in the IIOiIE register is set to 1.
Bits in the IIOiIR register are not set to 0 automatically even if an interrupt is accepted. They should be set
to 0 by either the AND or BCLR instruction. Note that every generated interrupt request is ignored until
these bit are set to 0.
To use the intelligent I/O interrupt to activate DMAC II, the IRLT bit in the IIOiIE register should be set to 0
(interrupt requests used for DMA or DMA II) and the bit for interrupt source to be used in the IIOiE register
should be set to 1 (interrupt enabled).
(1)
(1)
(1)
Rev.1.10
IIOiIR register
IIOiIE register
Bit 1
Bit 2
Bit 7
Bit 1
Bit 2
Bit 7
(2)
(3)
0
1
0
1
0
1
IRLT bit in the
IIOiIE register
Notes:
1. Refer to Figures 11.13 and 11.14 for bits 1
2. Bits 1 to 7 in the IIOiIR register are not set
3. The IRLT bit and the interrupt enable bit in
to 7 in registers IIOiIR and IIOiIE and
respective interrupt request sources.
to 0 automatically even if an interrupt
request is accepted. They should be set to
0 by a program.
the IIOiIE register should not be changed
simultaneously.
interrupt i request
Intelligent I/O
Page 163 of 604
11. Interrupts