R5F64175DFD#U0 Renesas Electronics America, R5F64175DFD#U0 Datasheet - Page 251
R5F64175DFD#U0
Manufacturer Part Number
R5F64175DFD#U0
Description
MCU 384+8KB FLASH 40K 144-LQFP
Manufacturer
Renesas Electronics America
Series
M16C/R32C/100/117r
Datasheet
1.R5F64176DFBU0.pdf
(639 pages)
Specifications of R5F64175DFD#U0
Core Processor
R32C/100
Core Size
16/32-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
120
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R32C/117 Group
REJ09B0533-0110
Sep 08, 2010
Figure 17.5
Three-Phase Output Buffer Register i
b7 b6 b5 b4
Note:
1. Values of registers IDB0 and IDB1 are transferred to the three-phase output shift register by a transfer
trigger. The initial output signal level of each phase is determined by the value written in the IDB0 register
after the transfer trigger occurs. After that, the output signal level is determined by the value written in the
IDB1 register on the falling edge of a one-shot pulse of timers A1, A2, and A4.
b3
Registers IDB0 and IDB1
b2
b1
Rev.1.10
b0
Bit Symbol
Symbol
IDB0, IDB1
(b7-b6)
DWBi
DUBi
DVBi
DWi
DUi
DVi
—
U-Phase Output Buffer i
U-Phase Output Buffer i
V-Phase Output Buffer i
V-Phase Output Buffer i
W-Phase Output Buffer i
W-Phase Output Buffer i
No register bits; should be written with 0 and read as undefined
value
Bit Name
(i = 0, 1)
Address
030Ah, 030Bh
(1)
These bits should be written with an
output level of the three-phase output
shift register. The written value is
reflected in each turn-on signal as
follows:
The bits are read as the value of the
three-phase output shift register
0: Active (ON)
1: Inactive (OFF)
17. Three-phase Motor Control Timers
Function
Reset Value
XX11 1111b
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