R5F64175DFD#U0 Renesas Electronics America, R5F64175DFD#U0 Datasheet - Page 410
R5F64175DFD#U0
Manufacturer Part Number
R5F64175DFD#U0
Description
MCU 384+8KB FLASH 40K 144-LQFP
Manufacturer
Renesas Electronics America
Series
M16C/R32C/100/117r
Datasheet
1.R5F64176DFBU0.pdf
(639 pages)
Specifications of R5F64175DFD#U0
Core Processor
R32C/100
Core Size
16/32-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
120
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R32C/117 Group
REJ09B0533-0110
Sep 08, 2010
24.1.8.8
Set the MST bit to select master or slave mode. To enter slave mode, set this bit to 0. Communication
is initiated in synchronization with the SCL clock generated by the master device. Set this bit to 1 to
enter master mode. The device generates the SCL clock to initiate communication.
The MST bit becomes 0 in any of the following cases:
• When the MST bit is set to 0
• When an arbitration lost is detected, and transmission of the corresponding byte is completed
• When a STOP condition is detected
• When a START condition is detected
• When the START condition redundancy prevention function is enabled
• When the ICE bit in the I2CCR0 register is set to 0 (I
• When the RST bit in the I2CCR0 register is written with 1 (I
MST Bit
Rev.1.10
2
C-bus interface disabled)
2
C-bus interface reset)
24. Multi-master I
Page 393 of 604
2
C-bus Interface
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