R5F64175DFD#U0 Renesas Electronics America, R5F64175DFD#U0 Datasheet - Page 543

• Manufacturer Part Number: R5F64175DFD#U0
• Description: MCU 384+8KB FLASH 40K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C/R32C/100/117r

Specifications of R5F64175DFD#U0

• Core Processor: R32C/100
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 120
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R32C/117 Group
REJ09B0533-0110
Sep 08, 2010
Table 27.13
Table 27.14
00b
01b
10b
11b
FSUW1 and
Bit Settings
00b
01b
10b
11b
FSUW1 and
Bit Settings
FSUW0
FSUW0
suw = 0
suw = 1
suw = 2
suw = 3
suw = 0
suw = 1
suw = 2
suw = 3
The Write Cycle and Bit Settings: MPY1, MPY0, FSUW1, FSUW0, FWW1, and FWW0,
When Peripheral Bus Clock is Divided by 3 (unit: cycles)
The Write Cycle and Bit Settings: MPY1, MPY0, FSUW1, FSUW0, FWW1, and FWW0,
When Peripheral Bus Clock is Divided by 4 (unit: cycles)
00b
01b
10b
00b
01b
10b
00b
01b
10b
00b
01b
10b
11b
11b
11b
11b
Rev.1.10
Bit Settings
FWW1and
00b
01b
10b
00b
01b
10b
00b
01b
10b
00b
01b
10b
11b
11b
11b
11b
FWW0
Bit Settings
FWW1and
FWW0
ww = 1
ww = 2
ww = 3
ww = 4
ww = 1
ww = 2
ww = 3
ww = 4
ww = 1
ww = 2
ww = 3
ww = 4
ww = 1
ww = 2
ww = 3
ww = 4
ww = 1
ww = 2
ww = 3
ww = 4
ww = 1
ww = 2
ww = 3
ww = 4
ww = 1
ww = 2
ww = 3
ww = 4
ww = 1
ww = 2
ww = 3
ww = 4
tsu
tsu
tsu
tsu
10
10
10
10
(S-W)
(A-W)
1
1
1
1
4
4
4
4
7
7
7
7
10
10
10
10
(S-W)
(A-W)
1
1
1
1
4
4
4
4
8
8
8
8
,
,
tw
12
12
12
12
3
6
9
3
6
9
3
6
9
3
6
9
(W)
tw
mpy = 3
12
12
11
12
3
6
9
3
6
9
2
5
8
3
6
9
(W)
10b
mpy = 3
10b
tc
12
15
12
15
18
12
15
18
21
15
18
21
24
MPY1 and MPY0 Bit Settings
6
9
9
W
tc
MPY1 and MPY0 Bit Settings
12
16
12
16
20
12
16
20
20
16
20
20
24
8
8
8
W
th
th
(W-S)
(W-A)
th
th
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
(W-S)
(W-A)
4
1
2
3
1
2
3
4
2
3
4
1
3
4
1
2
,
tsu
tsu
,
tsu
tsu
(S-W)
13
13
13
13
(A-W)
1
1
1
1
6
6
6
6
9
9
9
9
(S-W)
13
13
13
13
(A-W)
1
1
1
1
5
5
5
5
9
9
9
9
,
,
tw
12
16
15
12
16
12
16
11
4
8
3
7
4
8
4
8
(W)
tw
mpy = 4
12
16
12
16
12
16
12
16
4
8
4
8
4
8
4
8
(W)
11b
mpy = 4
11b
27. Flash Memory
tc
12
15
18
12
15
18
24
15
18
24
27
18
24
27
30
Page 526 of 604
6
W
tc
12
16
20
12
16
20
24
16
20
24
28
20
24
28
32
8
W
th
th
(W-S)
(W-A)
th
th
1
3
2
1
3
2
1
1
3
2
3
2
1
2
1
3
(W-S)
(W-A)
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
,
,