R5F64175DFD#U0 Renesas Electronics America, R5F64175DFD#U0 Datasheet - Page 88
R5F64175DFD#U0
Manufacturer Part Number
R5F64175DFD#U0
Description
MCU 384+8KB FLASH 40K 144-LQFP
Manufacturer
Renesas Electronics America
Series
M16C/R32C/100/117r
Datasheet
1.R5F64176DFBU0.pdf
(639 pages)
Specifications of R5F64175DFD#U0
Core Processor
R32C/100
Core Size
16/32-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
120
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R32C/117 Group
REJ09B0533-0110
Sep 08, 2010
5.2
5.3
5.4
Figure 5.4
A software reset is generated when the PM03 bit in the PM0 register is set to 1 (MCU is reset). When a
software reset is released, the CPU, SFRs, and pins are initialized. Then, the CPU starts executing the
program from the address indicated by the reset vector.
The PM03 bit should be set to 1 while the PLL clock is selected as the CPU clock source and the main
clock oscillation is completely stable.
Processor mode remains unchanged since bits PM01 and PM00 in the PM0 register are not affected by a
software reset.
A watchdog timer reset is generated when the watchdog timer underflows while the CM06 bit in the CM0
register is 1 (the MCU is reset if the watchdog timer underflows). When the watchdog timer reset is
released, the CPU, SFRs, and pins are initialized. Then, the CPU starts executing the program from the
address indicated by the reset vector.
Processor mode remains unchanged since bits PM01 and PM00 in the PM0 register are not affected by a
watchdog timer reset.
The reset vector in the R32C/100 Series is configured as shown in Figure 5.4.
The 32-bit start address of a program must be a multiple of 4. Because of this, the address always ends
with two zero bits. The reset vector contains the upper 30 bits of the start address in bits 2 to 31. Bits 0
and 1 of the reset vector are used to select the external bus width in microprocessor mode.
In single-chip mode, these bits should be set to 00b.
Note:
Content of reset vector
Software Reset
Watchdog Timer Reset
Reset Vector
Start address of the
1. The bits should be set to 00b in single-chip mode.
program
Reset Vector Configuration
FFFFFFFFh
FFFFFFFCh
FFFFFFFDh
FFFFFFFEh
Rev.1.10
b7
Upper 30 bits of reset vector
b0
External bus width select bits in microprocessor mode
0 0
32-bit bus width: 00b
16-bit bus width: 10b
8-bit bus width: 11b
(1)
Page 71 of 604
5. Resets
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