DF2372VFQ34V Renesas Electronics America, DF2372VFQ34V Datasheet - Page 849
DF2372VFQ34V
Manufacturer Part Number
DF2372VFQ34V
Description
IC H8S/2372 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2372VFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2372VFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 849 of 1208
- Download datasheet (8Mb)
Bit
4
3
2
1
0
Bit Name
NAKIE
STIE
ACKE
ACKBR
ACKBT
Initial Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
Description
NACK receive interrupt enable
This bit enables or disables the NACK receive
interrupt request (NAKI) when the NACKF and AL
bits in ICSR are set to 1. NAKI can be canceled by
clearing the NACKF, AL, or NAKIE bit to 0.
0: NACK receive interrupt request (NAKI) is
disabled.
1: NACK receive interrupt request (NAKI) is
enabled.
Stop condition detection interrupt enable
0: Stop condition detection interrupt request (STPI)
1: Stop condition detection interrupt request (STPI)
Acknowledge Bit Judgement Select
0: The value of the acknowledge bit is ignored, and
1: If the acknowledge bit is 1, continuous transfer is
Receive acknowledge
In transmit mode, this bit stores the acknowledge
data that are returned by the receive device. This
bit cannot be modified.
0: Receive acknowledge = 0
1: Receive acknowledge = 1
Transmit acknowledge
In receive mode, this bit specifies the bit to be sent
at the acknowledge timing.
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
is disabled.
is enabled.
continuous transfer is performed.
interrupted.
Section 16 I
Rev.7.00 Mar. 18, 2009 page 781 of 1136
2
C Bus Interface 2 (IIC2) (Option)
REJ09B0109-0700
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