HD64F2239FA16 Renesas Electronics America, HD64F2239FA16 Datasheet - Page 48
HD64F2239FA16
Manufacturer Part Number
HD64F2239FA16
Description
IC H8S MCU FLASH 384K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of HD64F2239FA16
Core Processor
H8S/2000
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239FA16V
Manufacturer:
RENESAS
Quantity:
1 000
Part Number:
HD64F2239FA16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Section 1 CPU
1.6.4
The H8S/2600 or H8S/2000 instructions consist of 2-byte (1-word) units. An instruction consists
of an operation field (op field), a register field (r field), an effective address extension (EA field),
and a condition field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first four bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers
by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement.
Condition Field: Specifies the branching condition of Bcc instructions.
Figure 1.12 shows examples of instruction formats.
Rev. 4.00 Feb 24, 2006 page 32 of 322
REJ09B0139-0400
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
(4) Operation field, effective address extension, and condition field
Basic Instruction Formats
op
op
op
cc
Figure 1.12 Instruction Formats
EA (disp)
op
rn
rn
EA (disp)
rm
rm
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm, etc.
BRA d:8, etc
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