R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet
R5F61668MZN50FPV
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R5F61668MZN50FPV Summary of contents
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REJ09B0596-0100 32 All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology ...
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Rev. 1.00 Jan. 29, 2010 Page ii of xxxii ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users ...
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Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this ...
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Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described ...
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Description of Abbreviations The abbreviations used in this manual are listed below. • Abbreviations specific to this product Abbreviation Description BSC Bus controller CPG Clock pulse generator DTC Data transfer controller INTC Interrupt controller PPG Programmable pulse generator SCI ...
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Section 1 Overview................................................................................................1 1.1 Features................................................................................................................................. 1 1.1.1 Applications .......................................................................................................... 1 1.1.2 Overview of Functions.......................................................................................... 2 1.2 List of Products................................................................................................................... 10 1.3 Block Diagram.................................................................................................................... 11 1.4 Pin Assignments ................................................................................................................. 12 1.4.1 Pin Assignments ................................................................................................. 12 1.4.2 Correspondence between Pin Configuration and ...
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Addressing Modes and Effective Address Calculation....................................................... 63 2.8.1 Register Direct—Rn ........................................................................................... 63 2.8.2 Register Indirect—@ERn................................................................................... 64 2.8.3 Register Indirect with Displacement —@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn).................................................................................................. 64 2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), ...
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Input/Output Pin ................................................................................................................. 89 4.3 Register Descriptions.......................................................................................................... 90 4.3.1 Reset Status Register (RSTSR)........................................................................... 90 4.3.2 Reset Control/Status Register (RSTCSR)........................................................... 92 4.4 Pin Reset ............................................................................................................................. 93 4.5 Power-on Reset (POR)........................................................................................................ 93 4.6 Power Supply Monitoring Reset ......................................................................................... 94 4.7 Deep ...
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Exception Handling by Illegal Instruction ........................................................ 118 6.8 Stack Status after Exception Handling ............................................................................. 119 6.9 Usage Note ....................................................................................................................... 120 Section 7 Interrupt Controller.............................................................................. 121 7.1 Features............................................................................................................................. 121 7.2 Input/Output Pins.............................................................................................................. 123 7.3 Register Descriptions........................................................................................................ 123 7.3.1 Interrupt Control ...
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Break Address Mask Register n (BAMRA, BAMRB, BAMRC, BAMRD) .... 165 8.3.3 Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD) ................... 166 8.4 Operation .......................................................................................................................... 168 8.4.1 Setting of Break Control Conditions................................................................. 168 8.4.2 PC Break........................................................................................................... 168 8.4.3 Condition ...
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I/O Pins Used for Basic Bus Interface .............................................................. 234 9.6.3 Basic Timing..................................................................................................... 235 9.6.4 Wait Control ..................................................................................................... 241 9.6.5 Read Strobe (RD) Timing................................................................................. 243 9.6.6 Extension of Chip Select (CS) Assertion Period............................................... 244 DACK and EDACK Signal Output Timing...................................................... ...
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Controlling Column Address Output Cycle...................................................... 273 9.10.7 Controlling Row Address Output Cycle ........................................................... 274 9.10.8 Controlling Precharge Cycle............................................................................. 276 9.10.9 Wait Control ..................................................................................................... 277 9.10.10 Controlling Byte and Word Accesses ............................................................... 280 9.10.11 Burst Access Operation..................................................................................... 282 9.10.12 Refresh ...
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Bus Controller Operation in Reset.................................................................................... 361 9.18 Usage Notes ...................................................................................................................... 361 Section 10 DMA Controller (DMAC)............................................................... 365 10.1 Features............................................................................................................................. 365 10.2 Input/Output Pins.............................................................................................................. 368 10.3 Register Descriptions........................................................................................................ 369 10.3.1 DMA Source Address Register (DSAR) .......................................................... 370 10.3.2 DMA Destination ...
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EXDMA Destination Address Register (EDDAR)........................................... 449 11.3.3 EXDMA Offset Register (EDOFR).................................................................. 450 11.3.4 EXDMA Transfer Count Register (EDTCR).................................................... 451 11.3.5 EXDMA Block Size Register (EDBSR)........................................................... 452 11.3.6 EXDMA Mode Control Register (EDMDR) .................................................... 453 11.3.7 EXDMA Address Control Register ...
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DTC Mode Register B (MRB).......................................................................... 551 12.2.3 DTC Source Address Register (SAR)............................................................... 552 12.2.4 DTC Destination Address Register (DAR)....................................................... 553 12.2.5 DTC Transfer Count Register A (CRA) ........................................................... 553 12.2.6 DTC Transfer Count Register B (CRB)............................................................ 554 12.2.7 DTC ...
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Section 13 I/O Ports ...........................................................................................583 13.1 Register Descriptions........................................................................................................ 591 13.1.1 Data Direction Register (PnDDR and M) ....... 592 13.1.2 Data Register (PnDR ...
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Notes on Port Function Control Register (PFCR) Settings............................... 665 Section 14 16-Bit Timer Pulse Unit (TPU) ....................................................... 667 14.1 Features............................................................................................................................. 667 14.2 Input/Output Pins.............................................................................................................. 671 14.3 Register Descriptions........................................................................................................ 672 14.3.1 Timer Control Register (TCR).......................................................................... 675 14.3.2 Timer Mode Register ...
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Conflict between Overflow/Underflow and Counter Clearing ......................... 751 14.10.12 Conflict between TCNT Write and Overflow/Underflow ................................ 751 14.10.13 Multiplexing of I/O Pins ................................................................................... 752 14.10.14 Interrupts in the Module Stop State .................................................................. 752 Section 15 Programmable Pulse Generator (PPG) ...
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Reset Input ........................................................................................................ 798 16.5 Operation Timing.............................................................................................................. 799 16.5.1 TCNT Count Timing ........................................................................................ 799 16.5.2 Timing of CMFA and CMFB Setting at Compare Match ................................ 800 16.5.3 Timing of Timer Output at Compare Match..................................................... 800 16.5.4 Timing of Counter ...
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Section 18 Watchdog Timer (WDT)..................................................................821 18.1 Features............................................................................................................................. 821 18.2 Input/Output Pin ............................................................................................................... 822 18.3 Register Descriptions........................................................................................................ 823 18.3.1 Timer Counter (TCNT)..................................................................................... 823 18.3.2 Timer Control/Status Register (TCSR)............................................................. 823 18.3.3 Reset Control/Status Register (RSTCSR)......................................................... 825 18.4 Operation .......................................................................................................................... 826 18.4.1 Watchdog ...
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Serial Data Transmission (Asynchronous Mode) ............................................. 880 19.4.6 Serial Data Reception (Asynchronous Mode) .................................................. 882 19.5 Multiprocessor Communication Function ........................................................................ 886 19.5.1 Multiprocessor Serial Data Transmission ......................................................... 888 19.5.2 Multiprocessor Serial Data Reception .............................................................. 889 19.6 Operation in Clocked ...
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Section 20 USB Function Module (USB)..........................................................925 20.1 Features............................................................................................................................. 925 20.2 Input/Output Pins.............................................................................................................. 926 20.3 Register Descriptions........................................................................................................ 927 20.3.1 Interrupt Flag Register 0 (IFR0) ....................................................................... 928 20.3.2 Interrupt Flag Register 1 (IFR1) ....................................................................... 930 20.3.3 Interrupt Flag Register 2 (IFR2) ....................................................................... ...
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Processing of USB Standard Commands and Class/Vendor Commands ......................... 982 20.6.1 Processing of Commands Transmitted by Control Transfer............................. 982 20.7 Stall Operations ................................................................................................................ 983 20.7.1 Overview .......................................................................................................... 983 20.7.2 Forcible Stall by Application ............................................................................ 983 20.7.3 Automatic Stall by ...
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Noise Canceler................................................................................................ 1019 21.4.7 Example of Use............................................................................................... 1020 21.5 Interrupt Request............................................................................................................. 1024 21.6 Bit Synchronous Circuit.................................................................................................. 1024 21.7 Usage Notes .................................................................................................................... 1025 Section 22 A/D Converter................................................................................1027 22.1 Features........................................................................................................................... 1027 22.2 Input/Output Pins............................................................................................................ 1030 22.3 Register Descriptions...................................................................................................... 1031 22.3.1 A/D ...
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Module Stop State Setting .............................................................................. 1062 23.5.2 D/A Output Hold Function in Software Standby Mode.................................. 1062 23.5.3 Notes on Deep Software Standby Mode ......................................................... 1062 Section 24 RAM .............................................................................................. 1063 Section 25 Flash Memory................................................................................ 1065 25.1 Features........................................................................................................................... 1065 25.2 ...
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Bypass Register (JTBPR) ............................................................................... 1167 26.4.3 Boundary Scan Register (JTBSR)................................................................... 1167 26.4.4 IDCODE Register (JTID) ............................................................................... 1173 26.5 Operations....................................................................................................................... 1174 26.5.1 TAP Controller ............................................................................................... 1174 26.5.2 Commands ...................................................................................................... 1175 26.6 Usage Notes .................................................................................................................... 1177 Section 27 Clock Pulse Generator ...
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Switching to Subclock .................................................................................... 1218 28.4 Module Stop State........................................................................................................... 1219 28.5 Sleep Mode ..................................................................................................................... 1219 28.5.1 Entry to Sleep Mode ....................................................................................... 1219 28.5.2 Exit from Sleep Mode..................................................................................... 1219 28.6 All-Module-Clock-Stop Mode........................................................................................ 1220 28.7 Software Standby Mode.................................................................................................. 1221 28.7.1 Entry ...
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Register States in Each Operating Mode ........................................................................ 1290 Section 30 Electrical Characteristics ...............................................................1307 30.1 Absolute Maximum Ratings ........................................................................................... 1307 30.2 DC Characteristics .......................................................................................................... 1308 30.3 AC Characteristics .......................................................................................................... 1311 30.3.1 Clock Timing .................................................................................................. 1311 30.3.2 Control Signal Timing .................................................................................... ...
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Rev. 1.00 Jan. 29, 2010 Page xxxii of xxxii ...
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Features The core of products in the H8SX/1668MZ Group of CISC (complex instruction set computer) microcontrollers is an H8SX CPU, which has an internal 32-bit architecture. The H8SX CPU provides upward-compatibility with the CPUs of other Renesas Technology-original microcontrollers; ...
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Section 1 Overview 1.1.2 Overview of Functions Table 1.1 lists the functions of these LSI products in outline. Table 1.2 shows the comparison of support functions in each group. Table 1.1 Overview of Functions Module/ Classification Function Memory ROM RAM ...
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Module/ Classification Function CPU MCU operating mode Power on reset (POR) Voltage detection circuit (LVD) Interrupt Interrupt (source) controller (INTC) Break interrupt (UBC) Description Mode 1: User boot mode (selected by driving the MD2 and MD1 pins low and driving ...
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Section 1 Overview Module/ Classification Function DMA EXDMA controller (EXDMAC) DMA controller (DMAC) Data transfer controller (DTC) External bus Bus extension controller (BSC) Rev. 1.00 Jan. 29, 2010 Page 4 of 1380 REJ09B0596-0100 Description • Two-channel DMA transfer available • ...
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Module/ Classification Function External bus Bus extension controller (BSC) Clock Clock pulse generator (CPG) Description Bus formats • External memory interfaces (for the connection of ROM, burst ROM, SRAM, byte control SRAM, DRAM, and synchronous DRAM) • Address/data bus format: ...
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Section 1 Overview Module/ Classification Function A/D converter A/D converter (ADC) D/A converter D/A converter (DAC) Timer 8-bit timer (TMR) Rev. 1.00 Jan. 29, 2010 Page 6 of 1380 REJ09B0596-0100 Description • 10-bit resolution × two units • Selectable input ...
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Module/ Classification Function Timer 16-bit timer pulse unit (TPU) Program- mable pulse generator (PPG) Watchdog timer Watchdog timer (WDT) 32K timer 32K timer (TM32K) Description • 16 bits × 6 channels • Select from among eight counter-input clocks for each ...
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Section 1 Overview Module/ Classification Function Serial interface Serial communi- cations interface (SCI) Smart card/SIM Universal serial Universal bus interface serial bus interface (USB bus interface I C bus interface 2 (IIC2) I/O ports Package Operating ...
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Table 1.2 Comparison of Support Functions in the H8SX/1668MZ Group Function DMAC DTC PPG UBC SCI IIC2 TMR WDT 10-bit ADC 8-bit DAC EXDMAC SDRAM interface 32K timer POR/LVD Package LQFP-144 H8SX/1668MZ Group ...
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... List of Products Table 1.3 is the list of products, and figure 1.1 shows how to read the product name code. Table 1.3 List of Products Group Part No. H8SX/1668MZ R5F61668MZN50FPV Group Part No 61668MZN50 FP Figure 1.1 How to Read the Product Name Code • Small Package Package Package Code PLQP0144KA-A (FP-144LV)* 20.0 × ...
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Block Diagram RAM ROM H8SX CPU DTC Main clock oscillator Subclock oscillator POR/LVD [Legend] CPU: Central processing unit DTC: Data transfer controller BSC: Bus controller DMAC: DMA controller EXDMAC: EXDMA controller TM32K: 32K timer WDT: Watchdog timer * Note: ...
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Section 1 Overview 1.4 Pin Assignments 1.4.1 Pin Assignments 108 107 106 105 104 103 102 101 100 109 P62/TMO2/SCK4/DACK2/IRQ10-B/TRST/EDACK0-B PLLV cc 110 111 P63/TMRI3/DREQ3/IRQ11-B/TMS/EDREQ1-B 112 PLLV ss 113 ...
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Correspondence between Pin Configuration and Operating Modes Table 1.4 Pin Configuration in Each Operating Mode Pin No. LQFP- 144 Modes 1, 2, and 6 1 PB1/CS1/CS2-B/ CS5-A/CS6-B/CS7-B 2 PB2/CS2-A/CS6-A/RAS 3 PB3/CS3-A/CS7-A/CAS 4 VSS 5 PB7/SDRAMφ 6 VCC 7 MD2 ...
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Section 1 Overview Pin No. LQFP- 144 Modes 1, 2, and 6 20 PE7/A15 21 PE6/A14 22 PE5/A13 23 Vss 24 PE4/A12 25 Vcc ⎯ PE3/A11 27 PE2/A10 28 PE1/A9 29 PE0/A8 30 PD7/A7 31 PD6/A6 32 Vss ...
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Pin No. LQFP- 144 Modes 1, 2, and 6 36 PD2/A2 37 PD1/A1 38 PD0/A0 39 EMLE ⎯ PM3 ⎯ PM4 42 DrVcc 43 USD+ ⎯ USD- ⎯ DrVss 46 VBUS ⎯ ...
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Section 1 Overview Pin No. LQFP- 144 Modes 1, 2, and 6 51 P21/PO1/TIOCA3/TMCI0/ RxD0/IRQ9-A 52 P22/PO2/TIOCC3/TMO0/ TxD0/IRQ10-A 53 P23/PO3/TIOCC3/TIOCD3/ IRQ11-A 54 P24/PO4/TIOCA4/TIOCB4/ TMRI1/SCK1 55 P25/PO5/TIOCA4/TMCI1/ RxD1 56 P30/PO8/TIOCA0/ DREQ0-B 57 P31/PO9/TIOCA0/TIOCB0/ TEND0-B 58 P32/PO10/TIOCC0/ TCLKA-A/DACK0-B 59 P26/PO6/TIOCA5/TMO1/ TxD1 60 ...
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Pin No. LQFP- 144 Modes 1, 2, and 6 72 PH6/D6 73 PH7/D7 ⎯ VSS 74 Vcc ⎯ PI0/D8 76 PI1/D9 77 PI2/D10 78 PI3/D11 79 Vss 80 PI4/D12 81 PI5/D13 82 PI6/D14 83 PI7/D15 84 P10/DREQ0-A/ IRQ0-A/EDREQ0-A ...
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Section 1 Overview Pin No. LQFP- 144 Modes 1, 2, and 6 92 VCL 93 P14/TCLKA-B/SDA1/ DREQ1-A/ IRQ4-A/EDREQ1-A 94 P15/TCLKB-B/SCL1/ TEND1-A/ IRQ5-A/ETEND1-A WDTOVF 95 96 Vss 97 XTAL 98 EXTAL ⎯ Vcc 100 P16/TCLKC-B/SDA0/ DACK1-A/ IRQ6-A/EDACK1-A 101 P17/TCLKD- ...
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Pin No. LQFP- 144 Modes 1, 2, and 6 111 P63/TMRI3/DREQ3/ IRQ11-B/EDREQ1-B ⎯ NC 112 PLLVss 113 P64/TMCI3/TEND3/ ETEND1-B 114 P65/TMO3/DACK3/ EDACK1-B 115 MD0 116 PC2/LUCAS/DQMLU 117 PC3/LLCAS/DQMLL ⎯ NC 118 P50/AN0/IRQ0-B 119 P51/AN1/IRQ1-B 120 P52/AN2/IRQ2-B ⎯ NC 121 Avcc ...
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Section 1 Overview Pin No. LQFP- 144 Modes 1, 2, and 6 130 PB4/CS4-B/WE 131 PB5/CS5-D/OE/CKE 132 PB6/CS6-D/ (RD/WR-B)/ADTRG0-B 133 MD3 134 PA0/BREQO/BS-A 135 PA1/BACK/(RD/WR-A) 136 PA2/BREQ/WAIT 137 PA3/LLWR/LLB 138 PA4/LHWR/LUB 139 PA5/RD 140 PA6/AS/AH/BS-B ⎯ Vcc 141 Vss 142 ...
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Pin Functions Table 1.5 Pin Functions Classification Pin Name Power supply PLLV CC PLLV SS DrV CC DrV SS Clock XTAL EXTAL OSC1 OSC2 Bφ SDRAMφ Operating mode MD3 to MD0 Input control ...
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Section 1 Overview Classification Pin Name Address bus A23 to A0 Data bus D15 to D0 BREQ Bus control BREQO BACK BS-A/BS RD/WR-A/RD/WR-B Output LHWR LLWR LUB LLB Rev. 1.00 Jan. 29, 2010 Page 22 of 1380 ...
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Classification Pin Name CS0 Bus control CS1 CS2-A/CS2-B CS3-A CS4-A/CS4-B CS5-A/CS5-B/ CS5-D CS6-A/CS6-B/ CS6-D CS7-A/CS7-B WAIT RAS CAS WE OE/CKE LUCAS LLCAS DQMLU DQMLL I/O Description Output Select signals for areas Input Requests wait cycles in access ...
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Section 1 Overview Classification Pin Name Interrupt NMI IRQ11-A/IRQ11-B IRQ10-A/IRQ10-B IRQ9-A/IRQ9-B IRQ8-A/IRQ8-B IRQ7-A/IRQ7-B IRQ6-A/IRQ6-B IRQ5-A/IRQ5-B IRQ4-A/IRQ4-B IRQ3-A/IRQ3-B IRQ2-A/IRQ2-B IRQ1-A/IRQ1-B IRQ0-A/IRQ0-B DREQ0-A/DREQ0-B DMA controller DREQ1-A/DREQ1-B (DMAC) DREQ2 DREQ3 DACK0-A/DACK0-B DACK1-A/DACK1-B DACK2 DACK3 TEND0-A/TEND0-B TEND1-A/TEND1-B TEND2 TEND3 Rev. 1.00 Jan. 29, 2010 ...
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Classification Pin Name EDREQ0-A/ EXDMA EDREQ0-B controller EDREQ1-A/ (EXDMAC) EDREQ1-B EDACK0-A/ EDACK0-B EDACK1-A/ EDACK1-B ETEND0-A/ ETEND0-B ETEND1-A/ ETEND1-B EDRAK0 EDRAK1 16-bit timer TCLKA-A/TCLKA-B pulse unit (TPU) TCLKB-A/TCLKB-B TCLKC-A/TCLKC-B TCLKD-A/TCLKD-B TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 ...
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Section 1 Overview Classification Pin Name 16-bit timer TIOCA5 pulse unit (TPU) TIOCB5 Programmable PO15 to PO0 pulse generator (PPG) 8-bit timer (TMR) TMO0 to TMO3 TMCI0 to TMCI3 TMRI0 to TMRI3 WDTOVF Watchdog timer (WDT) Serial TxD0 communications TxD1 ...
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Classification Pin Name A/D converter D/A converter AV SS Vref I/O ports P17 to P10 P27 to P20 P37 to P30 P57 to P50 P65 to P60 PA7 PA6 to PA0 PB7 to PB0 PC3 to PC2 PD7 ...
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Section 1 Overview Classification Pin Name I/O ports PJ7 to PJ0* PK7 to PK0* Note: * These pins can be used when the PCJKE bit in PFCRD is set single-chip mode. Rev. 1.00 Jan. 29, 2010 Page ...
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The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ...
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Section 2 CPU • Two base registers ⎯ Vector base register ⎯ Short address base register • 4-Gbyte address space ⎯ Program: 4 Gbytes ⎯ Data: 4 Gbytes • High-speed operation ⎯ All frequently-used instructions executed in one or two ...
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CPU Operating Modes The H8SX CPU has four operating modes: normal, middle, advanced and maximum modes. These modes can be selected by the mode pins of this LSI. CPU operating modes 2.2.1 Normal Mode The exception vector table and ...
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Section 2 CPU • Exception Vector Table and Memory Indirect Branch Addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The structure of the ...
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Middle Mode The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode. • Address Space The maximum address space of 16 Mbytes can be accessed as a total of the program ...
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Section 2 CPU 2.2.3 Advanced Mode The data area is extended to 4 Gbytes as compared with that in middle mode. • Address Space The maximum address space of 4 Gbytes can be linearly accessed. For individual areas ...
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Stack Structure The stack structure subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. Reserved SP (a) ...
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Section 2 CPU H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 Figure 2.6 Exception Vector Table (Maximum Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute ...
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Instruction Fetch The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes recommended that the mode be set according to the bus width of the memory in which a program is stored. The instruction-fetch ...
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Section 2 CPU 2.5 Registers The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register ...
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General Registers The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it ...
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Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine branches. Figure 2.11 shows the stack. SP (ER7) 2.5.2 Program Counter (PC) ...
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Condition-Code Register (CCR) CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask (I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can ...
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Section 2 CPU Initial Bit Bit Name Value 2 Z Undefined R Undefined R Undefined R/W 2.5.4 Extended Control Register (EXR) EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask ...
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Vector Base Register (VBR) VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are read as 0s. This register is a base address of the vector area for ...
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Section 2 CPU 2.6 Data Formats The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … ...
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Memory Data Formats Figure 2.13 shows the data formats in memory. The H8SX CPU can access word data and longword data which are stored at any addresses in memory. When word data begins at an odd address or longword ...
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Section 2 CPU 2.7 Instruction Set The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are called operation instruction in ...
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Function Instructions Branch BRA/BS, BRA/BC, BSR/BS, BSR/BC 4 Bcc* , JMP, BSR, JSR, RTS RTS/L BRA/S System control TRAPA, RTE, SLEEP, NOP RTE/L LDC, STC, ANDC, ORC, XORC [Legend] B: Byte size W: Word size L: Longword size Notes: 1. ...
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Section 2 CPU 2.7.1 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Classifi- cation Instruction Size Data MOV B/W/L ...
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Classifi- cation Instruction Size Arithmetic MULXS, B/W operations DIVXS MULS, DIVS W/L NEG B W/L EXTU, EXTS W/L TAS B 12 MAC* — 12 CLRMAC* — 12 LDMAC* — 12 STMAC* — Logic AND, OR, XOR B operations B B ...
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Section 2 CPU Classifi- cation Instruction Size Bit BFLD B manipu- BFST B lation 8 Branch BRA/BS, BRA/BC BSR/BS, BSR/BC* B System LDC B/W* control (CCR, EXR) LDC L (VBR, SBR) STC B/W* (CCR, EXR) STC L (VBR, ...
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Table 2.2 Combinations of Instructions and Addressing Modes (2) Classifi- cation Instruction Size — Branch BRA/BS, BRA/BC — BSR/BS, BSR/BC — Bcc — BRA — BRA/S — JMP — BSR — JSR — RTS, RTS/L — System TRAPA control — ...
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Section 2 CPU 2.7.2 Table of Instructions Classified by Function Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 2.3. Table 2.3 Operation Notation Operation Notation Description Rd ...
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Table 2.4 Data Transfer Instructions Instruction Size Function #IMM → (EAd), (EAs) → (EAd) MOV B/W/L Transfers data between immediate data, general registers, and memory. (EAs) → Rd MOVFPE B Rs → (EAs) MOVTPE B @SP+ → Rn POP W/L ...
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Section 2 CPU Table 2.5 Block Transfer Instructions Instruction Size Function EEPMOV.B B Transfers a data block. EEPMOV.W Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of ...
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Table 2.6 Arithmetic Operation Instructions Instruction Size Function (EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd) ADD B/W/L SUB Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data cannot be subtracted ...
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Section 2 CPU Instruction Size Function Rd ÷ Rs → Rd DIVU W/L Performs unsigned division on data in two general registers: either 16 bits ÷ 16 bits → 16-bit quotient bits ÷ 32 bits → 32-bit quotient. ...
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Table 2.7 Logic Operation Instructions Instruction Size Function (EAd) ∧ #IMM → (EAd), (EAd) ∧ (EAs) → (EAd) AND B/W/L Performs a logical AND operation on data between immediate data, general registers, and memory. (EAd) ∨ #IMM → (EAd), (EAd) ...
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Section 2 CPU Table 2.9 Bit Manipulation Instructions Instruction Size Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in the contents of a general register or a memory location to 1. The bit number is specified ...
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Instruction Size Function C ∨ [~ (<bit-No.> of <EAd>)] → C BIOR B ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in ...
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Section 2 CPU Instruction Size Function ∼ Z → (<bit-No.> of <EAd>) BISTZ B Transfers the inverse of the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit ...
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Table 2.11 System Control Instructions Instruction Size Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. RTE/L — Returns from an exception-handling routine, restoring data from the stack to multiple general registers. SLEEP — Causes ...
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Section 2 CPU 2.7.3 Basic Instruction Formats The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field ...
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Addressing Modes and Effective Address Calculation The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode ...
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Section 2 CPU 2.8.2 Register Indirect—@ERn The operand value is the contents of the memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. In ...
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Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn− • Register indirect with post-increment—@ERn+ The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ...
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Section 2 CPU Example 2: MOV.B @ER0+, @ER0+ When ER0 before execution is H'00001000, H'00001000 is read and the content is written at H'00001001. After execution, ER0 is H'00001002. 2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32 The operand value is ...
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Immediate—#xx The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. This addressing mode has short formats in which 3- or 4-bit immediate data can be used. When the size of immediate ...
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Section 2 CPU 2.8.10 Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed 8-bit absolute address in ...
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Extended Memory Indirect—@@vec:7 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: the sum of ...
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Section 2 CPU Table 2.14 Effective Address Calculation for Transfer and Operation Instructions No. Addressing Mode and Instruction Format 1 Immediate op IMM Register direct Register indirect Register indirect with 16-bit displacement ...
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Table 2.15 Effective Address Calculation for Branch Instructions No. Addressing Mode and Instruction Format Register indirect Program-counter relative with 8-bit displacement 2 op disp Program-counter relative with 16-bit displacement op disp Program-counter relative with index register 3 ...
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Section 2 CPU 2.9 Processing States The H8SX CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and program stop state. Figure 2.16 indicates the state transitions. • Reset state In this state ...
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RES = high Exception-handling state Request for exception End of exception handling handling Program execution state A transition to the reset state occurs whenever the STBY signal goes low. Note transition to the reset state occurs when the ...
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Section 2 CPU Rev. 1.00 Jan. 29, 2010 Page 74 of 1380 REJ09B0596-0100 ...
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Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI has seven operating modes (modes and 7). The operating mode is selected by the setting of mode pins MD2 to MD0. Enabling and ...
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Section 3 MCU Operating Modes Modes 1 and 2 are the user boot mode and the boot mode, respectively, in which the flash memory can be programmed and erased. For details on the user boot mode and boot mode, see ...
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Register Descriptions The following registers are related to the operating mode setting. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR indicates the current operating mode. When MDCR is read from, the ...
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Section 3 MCU Operating Modes Bit Bit Name Initial Value R/W 11 MDS3 Undefined* 10 MDS2 Undefined* 9 MDS1 Undefined* 8 MDS0 Undefined* ⎯ 7 Undefined* ⎯ ⎯ ⎯ ⎯ 3 Undefined* ⎯ 2 ...
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System Control Register (SYSCR) SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode. Bit 15 14 ⎯ ⎯ Bit Name Initial Value ...
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Section 3 MCU Operating Modes Initial Bit Bit Name Value ⎯ 10 Undefined 9 EXPE Undefined 8 RAME 1 ⎯ All 0 1 DTCMD 1 ⎯ Notes: 1. The initial value depends on the LSI ...
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Operating Mode Descriptions 3.3.1 Mode 1 This is the user boot mode for the flash memory. The LSI operates in the same way as in mode 7 except for programming and erasing of the flash memory. For details, see ...
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Section 3 MCU Operating Modes 3.3.5 Mode 5 The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on- chip ROM is disabled. The initial bus width mode immediately after a reset is ...
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Pin Functions Table 3.4 shows the pin functions in each operating mode. Table 3.4 Pin Functions in Each Operating Mode (Advanced Mode) MCU Port A Operating Mode PA7 PA6-3 PA2-0 1 P*/C P*/C P*/C 2 P*/C P*/C P*/C 3 ...
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Section 3 MCU Operating Modes Modes 1 and 2 User boot mode, boot mode (Advanced mode) H'000000 On-chip ROM H'100000 xternal address space reserved area* * H'FD9000 Access prohibited area H'FDC000 External address space reserved ...
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Mode 6 On-chip ROM enabled extended mode (Advanced mode) H'000000 On-chip ROM H'100000 External address space H'FD9000 Access prohibited area H'FDC000 External address space 1 H'FEC000 Reserved area* H'FEE000 On-chip RAM External address space H'FFC000 External address space ...
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Section 3 MCU Operating Modes Rev. 1.00 Jan. 29, 2010 Page 86 of 1380 REJ09B0596-0100 ...
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Types of Resets There are three types of resets: a pin reset, power-on reset, voltage-monitoring reset, deep software standby reset, and watchdog timer reset. Table 4.1 shows the reset names and sources. The internal state and pins are initialized ...
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Section 4 Resets RES Vcc Power-on reset circuit Voltage detection circuit Deep software standby reset generation circuit Watchdog timer Figure 4.1 Block Diagram of Reset Circuit Rev. 1.00 Jan. 29, 2010 Page 88 of 1380 REJ09B0596-0100 Pin reset Power-on reset ...
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Note that some registers are not initialized by any of the resets. The following describes the CPU internal registers. The PC, one of the CPU internal registers, is initialized by loading the start address from vector addresses with the reset ...
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Section 4 Resets 4.3 Register Descriptions This LSI has the following registers for resets. • Reset status register (RSTSR) • Reset control/status register (RSTCSR) 4.3.1 Reset Status Register (RSTSR) RSTSR indicates a source for generating an internal reset and voltage ...
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Initial Bit Bit Name Value 2 LVDF Undefined R/(W)* 1 — Undefined R/W 0 PORF Undefined R Note: Only 0 can be written to clear the flag. * R/W Description LVD Flag This bit indicates that the voltage detection circuit ...
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Section 4 Resets 4.3.2 Reset Control/Status Register (RSTCSR) RSTCSR controls an internal reset signal generated by the watchdog timer and selects the internal reset signal type. RSTCSR is initialized to H’ pin reset or a deep software standby ...
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Pin Reset This is a reset generated by the RES pin. When the RES pin is driven low, all the processing in progress is aborted and the LSI enters a reset state. In order to firmly reset the LSI, ...
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Section 4 Resets 1 Vpor* External power supply Vcc RES pin Vcc POR signal Vcc ("L" is valid) V Reset signal V Vcc ("L" is valid) Pin reset and OR signal for POR Set V Vcc PORF Notes: For details ...
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Deep Software Standby Reset This is an internal reset generated when deep software standby mode is canceled by an interrupt. When deep software standby mode is canceled, a deep software standby reset is generated, and simultaneously, clock oscillation starts. ...
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Section 4 Resets 4.9 Determination of Reset Generation Source Reading RSTCSR, RSTSR, or LVDCR of the voltage-detection circuit determines which reset was used to execute the reset exception handling. Figure 4.2 shows an example of the flow to identify a ...
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Section 5 Voltage Detection Circuit (LVD) This circuit is used to monitor Vcc. The LVD is capable of internally resetting the LSI when Vcc falls and crosses the voltage detection level. An interrupt can also be generated. 5.1 Features • ...
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Section 5 Voltage Detection Circuit (LVD) 5.2 Register Descriptions The registers of the voltage detection circuit are listed below. • Voltage detection control register (LVDCR) • Reset status register (RSTSR) 5.2.1 Voltage Detection Control Register (LVDCR) The LVDCR controls the ...
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Bit Bit Name Initial Value 4 LVDMON — 0 5.2.2 Reset Status Register (RSTSR) RSTSR indicates the source of an internal reset or voltage monitoring interrupt. Bit 7 6 Bit name DPSRSTF — Initial value: 0 ...
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Section 5 Voltage Detection Circuit (LVD) Bit Bit Name Initial Value — All 0 2 LVDF Undefined 1 — Undefined 0 PORF Undefined Note: To clear the flag, only 0 should be written to. * Rev. 1.00 ...
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Voltage Detection Circuit 5.3.1 Voltage Monitoring Reset Figure 5.2 shows the timing of a voltage monitoring reset by the voltage-detection circuit. When Vcc falls below Vdet in the state where the LVDE bit in LVDCR has been set to ...
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Section 5 Voltage Detection Circuit (LVD) 5.3.2 Voltage Monitoring Interrupt Figure 5.3 shows the timing of a voltage monitoring interrupt by the voltage-detection circuit. When Vcc falls below the Vdet in a state where the LVDE and LVDRI bits in ...
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Voltage monitoring interrupt (IRQ14) disabled Voltage detection and IRQ register settings If the flag has been set to 1 before the voltage-monitoring interrupt is enabled, clear it by writing 0 after having read Voltage-monitoring interrupt (IRQ14) enabled ...
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Section 5 Voltage Detection Circuit (LVD) 5.3.3 Release from Deep Software Standby Mode by the Voltage-Detection Circuit If the LVDE and LVDRI bits in LVDCR and the DLVDIE bit in DPSIER have all been set to 1 during a period ...
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Section 6 Exception Handling 6.1 Exception Handling Types and Priority As table 6.1 indicates, exception handling is caused by a reset, a trace, an address error, an interrupt, a trap instruction, a sleep instruction, and an illegal instruction (general illegal ...
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Section 6 Exception Handling 6.2 Exception Sources and Exception Handling Vector Table Different vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the contents of the vector base register (VBR) and vector ...
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Exception Source Reserved for system use User area (not used) External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 Reserved for system use 4 Internal interrupt* Notes: 1. Lower 16 bits of the address. 2. ...
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Section 6 Exception Handling Table 6.3 Calculation Method of Exception Handling Vector Table Address Exception Source Calculation Method of Vector Table Address Reset, CPU address error Vector table address = (vector table address offset) Vector table address = VBR + ...
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Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, ...
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Section 6 Exception Handling Bφ RES Address bus RD HWR, LWR D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start ...
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Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit must be cleared. For ...
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Section 6 Exception Handling 6.5 Address Error 6.5.1 Address Error Source Instruction fetch, stack operation, or data read/write shown in table 6.5 may cause an address error. Table 6.5 Bus Cycle and Address Error Bus Cycle Type Bus Master Instruction ...
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Bus Cycle Type Bus Master Data read/write EXDMAC Single address DMAC or transfer EXDMAC Notes: 1. For on-chip peripheral module space, see section 9, Bus Controller (BSC). 2. For the access prohibited area, refer to figure 3.1 in section 3.4, ...
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Section 6 Exception Handling When an address error occurs, the following is performed to halt the DTC, DMAC, and EXDMAC. • The ERR bit of DTCCR in the DTC is set to 1. • The ERRF bit of DMDR_0 in ...
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Interrupts 6.6.1 Interrupt Sources Interrupt sources are NMI, IRQ0 to IRQ11, and on-chip peripheral modules, as shown in table 6.7. Table 6.7 Interrupt Sources Type Source NMI NMI pin (external input) UBC break UBC break controller (UBC) interrupt Pins ...
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Section 6 Exception Handling The interrupt exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared ...
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Sleep Instruction Exception Handling The sleep instruction exception handling starts when a sleep instruction is executed with the SSBY bit in SBYCR set to 0 and the SLPIE bit in SBYCR set to 1. The sleep instruction exception handling ...
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Section 6 Exception Handling 6.7.3 Exception Handling by Illegal Instruction The illegal instructions are general illegal instructions and slot illegal instructions. The exception handling by the general illegal instruction starts when an undefined code is executed. The exception handling by ...
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Stack Status after Exception Handling Figure 6.3 shows the stack after completion of exception handling. Advanced mode SP Interrupt control mode 0 Note: * Ignored on return. Figure 6.3 Stack Status after Exception Handling SP CCR PC (24 bits) ...
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Section 6 Exception Handling 6.9 Usage Note When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value ...
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Section 7 Interrupt Controller 7.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the interrupt control register (INTCR). • Priority can be assigned by the ...
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Section 7 Interrupt Controller A block diagram of the interrupt controller is shown in figure 7.1. INTCR NMI input IRQ11 to 0 input TM32K IRQ15 input LVD IRQ14 input Internal interrupt sources WOVI to RESUME [Legend] Interrupt control register INTCR: ...
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Input/Output Pins Table 7.1 shows the pin configuration of the interrupt controller. Table 7.1 Pin Configuration Name I/O NMI Input IRQ11 to IRQ0 Input 7.3 Register Descriptions The interrupt controller has the following registers. • Interrupt control register (INTCR) ...
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Section 7 Interrupt Controller 7.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the edge to detect NMI. Bit 7 6 ⎯ ⎯ Bit Name Initial Value Initial Bit Bit Name Value ...
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CPU Priority Control Register (CPUPCR) CPUPCR sets whether or not the CPU has priority over the DTC, DMAC and EXDMAC. The interrupt exception handling by the CPU can be given priority over that of the DTC, DMAC and EXDMAC ...
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Section 7 Interrupt Controller Initial Bit Bit Name Value 3 IPSETE 0 2 CPUP2 0 1 CPUP1 0 0 CPUP0 0 Note: When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits * ...
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Interrupt Priority Registers and R (IPRA to IPRO, IPRQ, and IPRR) IPR sets priory (levels for interrupts other than NMI. Setting a value in the range from B'000 to B'111 in the ...
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Section 7 Interrupt Controller Initial Bit Bit Name Value 10 IPR10 1 9 IPR9 1 8 IPR8 1 ⎯ IPR6 1 5 IPR5 1 4 IPR4 1 ⎯ IPR2 1 1 IPR1 1 0 ...
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IRQ Enable Register (IER) IER enables interrupt requests IRQ15, IRQ14, and IRQ11 to IRQ0. Bit 15 14 Bit Name IRQ15E IRQ14E Initial Value 0 0 R/W R/W R/W Bit 7 6 Bit Name IRQ7E IRQ6E Initial Value 0 0 ...
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Section 7 Interrupt Controller Initial Bit Bit Name Value 7 IRQ7E 0 6 IRQ6E 0 5 IRQ5E 0 4 IRQ4E 0 3 IRQ3E 0 2 IRQ2E 0 1 IRQ1E 0 0 IRQ0E 0 7.3.5 IRQ Sense Control Registers H and ...
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ISCRH Bit 15 14 Bit Name IRQ15SR IRQ15SF Initial Value 0 0 R/W R/W R Bit Bit Name IRQ11SR IRQ11SF Initial Value 0 0 R/W R/W R/W • ISCRL Bit 15 14 Bit Name IRQ7SR IRQ7SF Initial ...
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Section 7 Interrupt Controller Initial Bit Bit Name Value 13 IRQ14SR 0 IRQ14SF ⎯ All 0 7 IRQ11SR 0 6 IRQ11SF 0 5 IRQ10SR 0 4 IRQ10SF 0 Rev. 1.00 Jan. 29, 2010 Page 132 ...
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Initial Bit Bit Name Value 3 IRQ9SR 0 2 IRQ9SF 0 1 IRQ8SR 0 0 IRQ8SF 0 R/W Description R/W IRQ9 Sense Control Rise R/W IRQ9 Sense Control Fall 00: Interrupt request generated by low level of IRQ9 01: Interrupt ...
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Section 7 Interrupt Controller • ISCRL Initial Bit Bit Name Value 15 IRQ7SR 0 14 IRQ7SF 0 13 IRQ6SR 0 12 IRQ6SF 0 11 IRQ5SR 0 10 IRQ5SF 0 9 IRQ4SR 0 8 IRQ4SF 0 7 IRQ3SR 0 6 IRQ3SF ...
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Initial Bit Bit Name Value 5 IRQ2SR 0 4 IRQ2SF 0 3 IRQ1SR 0 2 IRQ1SF 0 1 IRQ0SR 0 0 IRQ0SF 0 R/W Description R/W IRQ2 Sense Control Rise IRQ2 Sense Control Fall R/W 00: Interrupt request generated by ...
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Section 7 Interrupt Controller 7.3.6 IRQ Status Register (ISR) ISR is an IRQ15, IRQ14, and IRQ11 to IRQ0 interrupt request register. Bit 15 14 Bit Name IRQ15F IRQ14F Initial Value 0 0 R/W R/(W)* R/(W)* Bit 7 6 Bit Name ...
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Initial Bit Bit Name Value 11 IRQ11F 0 10 IRQ10F 0 9 IRQ9F 0 8 IRQ8F 0 7 IRQ7F 0 6 IRQ6F 0 5 IRQ5F 0 4 IRQ4F 0 3 IRQ3F 0 2 IRQ2F 0 1 IRQ1F 0 0 IRQ0F ...
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Section 7 Interrupt Controller Initial Bit Bit Name Value 15 SSI15 0 ⎯ All 0 11 SSI11 0 10 SSI10 0 9 SSI9 0 8 SSI8 0 7 SSI7 0 6 SSI6 0 5 SSI5 0 4 ...
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Interrupt Sources 7.4.1 External Interrupts There are thirteen external interrupts: NMI and IRQ11 to IRQ0. These interrupts can be used to leave software standby mode. (1) NMI Interrupts Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always ...
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Section 7 Interrupt Controller Detection of IRQn interrupts is enabled through the P1ICR, P2ICR, and P5ICR register settings, and does not change regardless of the output setting. However, when a pin is used as an external interrupt input pin, the ...
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Interrupt Exception Handling Vector Table Table 7.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. In the default priority order, a lower vector number corresponds to a higher priority. When interrupt control mode 2 is set, ...
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Section 7 Interrupt Controller Vector Classification Interrupt Source Number ⎯ Reserved for 80 system use WDT WOVI 81 ⎯ Reserved for 82 system use Refresh CMI 83 controller ⎯ Reserved for 84 system use 85 A/D_0 ADI0 86 ⎯ Reserved ...
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Vector Classification Interrupt Source Number TPU_4 TGI4A 106 TGI4B 107 TCI4V 108 TCI4U 109 TPU_5 TGI5A 110 TGI5B 111 TCI5V 112 TCI5U 113 ⎯ Reserved for 114 system use 115 TMR_0 CMI0A 116 CMI0B 117 OV0I 118 TMR_1 CMI1A 119 ...
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Section 7 Interrupt Controller Vector Classification Interrupt Source Number EXDMAC EXDMTEND0 132 EXDMTEND1 133 DMAC DMEEND0 136 DMEEND1 137 DMEEND2 138 DMEEND3 139 EXDMAC EXDMEEND0 140 EXDMEEND1 141 SCI_0 ERI0 144 RXI0 145 TXI0 146 TEI0 147 SCI_1 ERI1 148 ...
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Vector Classification Interrupt Source Number ⎯ Reserved for 192 system use | 215 IIC2_0 IICI0 216 ⎯ Reserved for 217 system use IIC2_1 IICI1 218 ⎯ Reserved for 219 system use SCI_6 RXI6 224 TXI6 225 ERI6 226 TEI6 227 ...
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Section 7 Interrupt Controller 7.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control ...
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The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. IRQ0 Figure 7.3 Flowchart of Procedure ...
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Section 7 Interrupt Controller 7.6.2 Interrupt Control Mode 2 In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the interrupt mask level ( bits) in EXR of the CPU and the IPR setting. ...
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Program execution state Interrupt generated? Yes No Level 7 interrupt? Yes Level 6 interrupt? No Mask level 6 or below? Yes Mask level 5 Save PC, CCR, and EXR Clear T bit to 0 Update mask level Read vector address ...
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Section 7 Interrupt Controller 7.6.3 Interrupt Exception Handling Sequence Figure 7.5 shows the interrupt exception handling sequence. The example is for the case where interrupt control mode 0 is set in maximum mode, and the program area and stack area ...
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Interrupt Response Times Table 7.4 shows interrupt response times – the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols for execution states used in table 7.4 are ...
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Section 7 Interrupt Controller Table 7.5 Number of Execution States in Interrupt Handling Routine On-Chip Symbol Memory Vector fetch Instruction fetch Stack manipulation [Legend] m: Number of wait cycles in an ...
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Figure 7.6 shows a block diagram of the DTC, DMAC and interrupt controller. Interrupt request DMAC On-chip select peripheral circuit Interrupt request module clear signal Interrupt request IRQ Interrupt request interrupt clear signal Interrupt controller Figure 7.6 Block Diagram of ...
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Section 7 Interrupt Controller to the DTCP and DMAP setting. If the CPU is given priority over the DTC or DMAC, the DTC or DMAC may not be activated, and the data transfer may not be performed. (2) Priority Determination ...
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To initiate multiple channels for the DTC and DMAC with the same interrupt, the same priority (DTCP = DMAP) should be assigned. 7.7 CPU Priority Control Function Over DTC, DMAC and EXDMAC The interrupt controller has a function to control ...
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Section 7 Interrupt Controller the condition that has held the activation source is cancelled (CPUPCE = 1 and the value of the bits CPUP2 to CPUP0 is greater than that of the bits EDMAP2 to EDMAP0). When different priority level ...
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Table 7.8 shows a setting example of the priority control function over the DTC, DMAC and EXDMAC, and the transfer request control state. A priority level can be independently set to each DMAC and EXDMAC channel, but the table only ...
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Section 7 Interrupt Controller 7.8 Usage Notes 7.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared mask the interrupt, the masking becomes effective after execution of the instruction. When an interrupt enable ...
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Instructions that Disable Interrupts Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the ...
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Section 7 Interrupt Controller 7.8.6 Interrupts of Peripheral Modules To clear an interrupt source flag by the CPU using an interrupt function of a peripheral module, the flag must be read from after clearing within the interrupt processing routine. This ...
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Section 8 User Break Controller (UBC) The user break controller (UBC) generates a UBC break interrupt request each time the state of the program counter matches a specified break condition. The UBC break interrupt is a non- maskable interrupt and ...
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Section 8 User Break Controller (UBC) 8.2 Block Diagram Instruction execution pointer Instruction execution pointer Mode control BARAH BARAL Break address Break BARBH BARBL control BARCH BARCL BARDH BARDL BRCRA BRCRB BRCRC BRCRD [Legend] BARAH, BARAL: Break address register A ...
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Register Descriptions Table 8.1 lists the register configuration of the UBC. Table 8.1 Register Configuration Register Name Break address register A Break address mask register A Break address register B Break address mask register B Break address register C ...
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Section 8 User Break Controller (UBC) 8.3.1 Break Address Register n (BARA, BARB, BARC, BARD) Each break address register n (BARn) consists of break address register nH (BARnH) and break address register nL (BARnL). Together, BARnH and BARnL specify the ...
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Break Address Mask Register n (BAMRA, BAMRB, BAMRC, BAMRD) Be sure to write H'FF00 0000 to break address mask register n (BAMRn). Operation is not guaranteed if another value is written here. BAMRnH Bit BAMRn31 ...
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Section 8 User Break Controller (UBC) 8.3.3 Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD) BRCRA, BRCRB, BRCRC, and BRCRD are used to specify and control conditions for channels and D of the UBC ...
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Initial Bit Bit Name Value 5 IDn1 0 4 IDn0 0 3 RWn1 0 2 RWn0 0 ⎯ ⎯ [Legend Channels Section 8 User Break Controller (UBC) R/W Description R/W Break ...
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Section 8 User Break Controller (UBC) 8.4 Operation The UBC does not detect condition matches in standby states (sleep mode, all module clock stop mode, software standby mode, deep software standby, and hardware standby mode). 8.4.1 Setting of Break Control ...