DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 136
DF2398TE20
Manufacturer Part Number
DF2398TE20
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2398TE20
HD64F2398TE20
HD64F2398TE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.1.3
Table 6-1 summarizes the pins of the bus controller.
Table 6-1
Rev.6.00 Oct.28.2004 page 106 of 1016
REJ09B0138-0600H
Pin Configuration
Name
Address strobe
Read
High write/write enable
Low write
Chip select 0
Chip select 1
Chip select 2/row address
strobe 2
Chip select 3/row address
strobe 3
Chip select 4/row address
strobe 4
Chip select 5/row address
strobe 5
Chip select 6
Chip select 7
Upper column address strobe
Lower column strobe
Wait
Bus request
Bus request acknowledge
Bus request output
Bus Controller Pins
Symbol I/O
AS
RD
HWR
LWR
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CAS
LCAS
WAIT
BREQ
BACK
BREQO Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Output
Function
Strobe signal indicating that address output on
address bus is enabled.
Strobe signal indicating that external space is
being read.
Strobe signal indicating that external space is to
be written, and upper half (D
enabled.
2-CAS DRAM write enable signal.
Strobe signal indicating that external space is to
be written, and lower half (D
enabled.
Strobe signal indicating that area 0 is selected.
Strobe signal indicating that area 1 is selected.
Strobe signal indicating that area 2 is selected.
DRAM row address strobe signal when area 2 is
in DRAM space.
Strobe signal indicating that area 3 is selected.
DRAM row address strobe signal when area 3 is
in DRAM space.
Strobe signal indicating that area 4 is selected.
DRAM row address strobe signal when area 4 is
in DRAM space.
Strobe signal indicating that area 5 is selected.
DRAM row address strobe signal when area 5 is
in DRAM space.
Strobe signal indicating that area 6 is selected.
Strobe signal indicating that area 7 is selected.
2-CAS DRAM upper column address strobe
signal.
DRAM lower column address strobe signal.
Wait request signal when accessing external 3-
state access space.
Request signal that releases bus to external
device.
Acknowledge signal indicating that bus has been
released.
External bus request signal used when internal
bus master accesses external space when
external bus is released.
7
15
to D
to D
0
) of data bus is
8
) of data bus is
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