DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 410
DF2398TE20
Manufacturer Part Number
DF2398TE20
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2398TE20
HD64F2398TE20
HD64F2398TE20
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
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Example of Buffer Operation Setting Procedure: Figure 10-18 shows an example of the buffer operation setting
procedure.
Examples of Buffer Operation
Rev.6.00 Oct.28.2004 page 380 of 1016
REJ09B0138-0600H
When TGR is an output compare register
Figure 10-19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer
operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare
match B, 1 output at compare match A, and 0 output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register
TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare
match A occurs.
For details of PWM modes, see section 10.4.6, PWM Modes.
TGR0B
TGR0A
H'0000
TGR0C
TGR0A
TIOCA
TCNT value
Transfer
Select TGR function
Set buffer operation
<Buffer operation>
H'0200
Buffer operation
Start count
Figure 10-18 Example of Buffer Operation Setting Procedure
H'0200
Figure 10-19 Example of Buffer Operation (1)
H'0200
[1]
[2]
[3]
H'0450
[1] Designate TGR as an input capture register or
[2] Designate TGR for buffer operation with bits
[3] Set the CST bit in TSTR to 1 to start the count
output compare register by means of TIOR.
BFA and BFB in TMDR.
operation.
H'0450
H'0450
H'0520
H'0520
Time
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