DF2377RVFQ33 Renesas Electronics America, DF2377RVFQ33 Datasheet - Page 857
DF2377RVFQ33
Manufacturer Part Number
DF2377RVFQ33
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2377RVFQ33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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16.4.3
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. The reception procedure and operations in master
receive mode are shown below.
1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCRA to 0 to switch from master
2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,
3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise
4. The continuous reception is performed by reading ICDRR and clearing RDRF to 0 every time
5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR.
6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, read ICDRR. Then, clear
7. When the STOP bit in ICSR is set to 1, read ICDRR and clear RDRF to 0. Then clear the
8. The operation returns to the slave receive mode.
transmit mode to master receive mode. Then, clear the TDRE bit to 0.
and data received, in synchronization with the internal clock. The master device outputs the
level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.
of 9th receive clock pulse. At this time, the received data is read by reading ICDRR.
RDRF is set. If 8th receive clock pulse falls after reading ICDRR by the other processing while
RDRF is 1, SCL is fixed low until ICDRR is read.
This enables the issuance of the stop condition after the next reception.
RCVD.
RCVD bit to 0.
Master Receive Operation
Section 16 I
Rev.7.00 Mar. 18, 2009 page 789 of 1136
2
C Bus Interface 2 (IIC2) (Option)
REJ09B0109-0700
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