M30878FJBGP#U5 Renesas Electronics America, M30878FJBGP#U5 Datasheet - Page 431
M30878FJBGP#U5
Manufacturer Part Number
M30878FJBGP#U5
Description
IC M32C/87 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M30878FJBGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30878FJBGP#U5M30878FJBGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 407 of 587
23.1.1.4
23.1.1.5
23.1.1.6
Bits TSPRE1 and TSPRE0 determine the count source of the time stamp counter.
NOTE:
When the TSRESET bit is set to 1 (count reset), the CiTSR register becomes 0000h. The TSRESET bit is
automatically set back to 0 after the CiTSR register becomes 0000h.
When the ECRESET bit is set to 1, registers CiTEC and CiREC become 00h and the CAN module are forcibly
placed in an error active state.
The ECRESET bit is automatically set back to 0 after the CAN module enters an error active state.
NOTES:
1. Change bits TSPRE1 and TSPRE0 setting while the STATE_RESET bit is 1 (CAN module is in reset).
1. Once entering an error active state, the CAN module is permitted to communicate after 11 consecutive
2. Set the ECRESET bit to 1 while the CAN module is in a bus-off or bus-idle state. Do not set the
recessive bits have been detected on the CAN bus.
ECRESET bit to 1 while the CAN module is transmitting or receiving.
TSPRE1 and TSPRE0 Bits
TSRESET Bit
ECRESET Bit
23. CAN Module
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