HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 192
HD6417708RF100A
Manufacturer Part Number
HD6417708RF100A
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708RF100A
Core Processor
SH-2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3.15 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
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Quantity:
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HD6417708RF100AV
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Bits 1 and 0—Peripheral Clock Frequency Division Ratio (PFC1, PFC0): These bits specify the
division ratio of the peripheral clock frequency with respect to the frequency of the output
frequency of PLL circuit 1 or the frequency of the CKIO pin.
Bit 1: PFC1
0
0
1
1
Note: Do not set the peripheral clock frequency higher than the frequency of the CKIO pin.
SH7708R:
Bits 15, 5 and 4—Frequency Multiplication Ratio (STC): These bits specify the frequency
multiplication ratio of PLL circuit 1.
Bit 15: STC2
0
0
1
1
Note: Do not set the output frequency of PLL circuit 1 higher than 100MHz.
Bits 14, 3 and 2—Internal Clock Frequency Division Ratio (IFC): These bits specify the frequency
division ratio of the internal clock with respect to the output frequency of PLL circuit 1. When
PLL circuit 1 is off or in standby mode, set
172
Initial value:
Initial value:
Bit name:
Bit name:
R/W:
R/W:
Bit:
Bit:
Bit 0: PFC0
0
1
0
1
Bit 5: STC1
0
0
0
1
PLLEN
STC2
R/W
R/W
15
0
7
0
PSTBY
IFC2
R/W
R/W
14
0
6
0
Description
Setting prohibited (do not set)
Bit 4: STC0
0
1
0
0
1
1/2
1/4
PFC2
STC1
R/W
R/W
13
0
5
0
1.
STC0
R/W
Description
12
—
0
R
4
0
1
2
3
4
IFC1
R/W
11
—
0
R
3
0
IFC0
R/W
10
—
0
R
2
0
PFC1
R/W
—
9
0
R
1
1
(Initial value)
(Initial value)
CKOEN
PFC0
R/W
R/W
8
1
0
0
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