M30878FJAGP#U5 Renesas Electronics America, M30878FJAGP#U5 Datasheet - Page 101
M30878FJAGP#U5
Manufacturer Part Number
M30878FJAGP#U5
Description
IC M32C/87 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M30878FJAGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30878FJAGP#U5M30878FJAGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 77 of 587
Figure 8.10
8.2.5
8.2.6
Table 8.7
Clock generation circuits
RD, WR, A0 to A22, A23, D0 to D15, CS0 to CS3, ALE,
HLDA, programmable I/O ports
Internal peripheral circuits
A0/D0 to A7/D7
The ALE output signal is provided for the external devices to latch the address when using the multiplexed bus.
Latch the address at the falling edge of the ALE output. Bits PM15 and PM14 in the PM1 register determine to
what pin the ALE output is assigned.
The ALE signal is output even when accessing the internal space.
The RDY signal facilitates access to external devices requiring longer access time. When RDY input is “L” at
the falling edge of the last BCLK cycle, wait states are inserted into the bus cycle. Then, when an “H” signal is
input to the RDY pin at the falling edge of BCLK, the MCU resumes executing the remaining bus clock.
Table 8.7 lists MCU states when placed in wait state by RDY input. Figure 8.11 shows an example of the RD
signal that is extended by the RDY signal.
A16 to A19
(1) 8-bit data bus
A8 to A15
A20/CS3
A21/CS2
A22/CS1
A23/CS0
ALE Output
NOTES:
RDY Input
ALE
1. A0/D0 to A15/D15 are placed in high-impedance states when read.
2. When the multiplexed bus is selected for all CS areas, A16 to A19 become I/O ports.
ALE Output and Address/Data Bus
MCU States while “L” is Input to the RDY Pin
Address
Address or CS
Item
Address
Address
(2)
Data
(1)
Operating (oscillating)
Maintains the same state as when “L” is input to RDY pin.
Operating
A0/D0 to A15/D15
A16 to A19
(2) 16-bit data bus
A20/CS3
A21/CS2
A22/CS1
A23/CS0
ALE
Address
Address or CS
Address
State
(2)
Data
(1)
8. Bus
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