M30878FJAGP#U5 Renesas Electronics America, M30878FJAGP#U5 Datasheet - Page 523
M30878FJAGP#U5
Manufacturer Part Number
M30878FJAGP#U5
Description
IC M32C/87 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M30878FJAGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30878FJAGP#U5M30878FJAGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 499 of 587
26.3.1.3
26.3.1.4
26.3.1.5
26.3.1.6
26.3.1.7
Figure 26.8 shows a flow chart illustrating entering and exiting low power mode. Follow the procedure on the flow
chart.
The flash memory is automatically turned off when entering wait mode or stop mode, and turned back on when
exiting wait mode or stop mode. Set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled)
before entering wait mode or stop mode.
•
•
The lock bit becomes invalid by setting the FMR02 bit to 1 (lock bit disabled). (Refer to 26.3.3 Data Protect
Function for details.) The lock bit becomes valid by setting the FMR02 bit to 0 (lock bit enabled).
The FMR02 bit does not change a lock bit status but disables a lock bit function. When the block erase
command is executed while the FMR02 bit is set to 1, the lock bit status changes from 0 (locked) to 1
(unlocked).
The FMSTP bit is used to initialize the flash memory control circuits, and also to reduce power consumption in
the flash memory. Access to the flash memory is disabled when the FMSTP bit is set to 1 (flash memory
stopped). Set the FMSTP bit to 1 by the program placed in an area other than the flash memory.
Set the FMSTP bit to 1 in one of the following cases:
The FMR05 bit selects access to either the boot ROM area or user ROM area in boot mode. Set to 0 to access
(read) the boot ROM area or set to 1 to access (read, write, or erase) the user ROM area.
The FMR06 bit is a read-only bit indicating the status of a program operation. The FMR06 bit becomes 1 when
a program error occurs; otherwise, it is 0. Refer to 26.3.5 Full Status Check for details.
The FMR07 bit is a read-only bit indicating the status of an erase operation. The FMR07 bit becomes 1 when an
erase error occurs; otherwise, it is 0. Refer to 26.3.5 Full Status Check for details.
A flash memory access error occurs while erasing or programming in EW0 mode (the FMR00 bit does not
switch back to 1 (ready)).
To further reduce power consumption in low-power consumption mode or on-chip oscillator low-power
consumption mode.
FMR02 Bit
FMSTP Bit
FMR05 Bit
FMR06 Bit
FMR07 Bit
26. Flash Memory
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