HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 606
HD6417727BP100BV
Manufacturer Part Number
HD6417727BP100BV
Description
IC SUPERH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP100BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Section 18 Smart Card Interface
Bits 3 to 0—These bits have the same function as in the ordinary SCI. See section 17, Serial
Communication Interface (SCI), for more information. The setting conditions for bit 2, the
transmit end bit (TEND), are changed as follows.
Bit 2: TEND
0
1
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
18.3
18.3.1
The primary functions of the smart card interface are described below.
1. Each frame consists of 8-bit data and 1 parity bit.
2. During transmission, the card leaves a guard time of at least 2 etu (elementary time units: time
3. During reception, the card outputs an error signal low level for 1 etu after 10.5 etu has elapsed
4. During transmission, it automatically transmits the same data after allowing at least 2 etu from
5. Only start-stop type asynchronous communication functions are supported; no synchronous
Rev.6.00 Mar. 27, 2009 Page 548 of 1036
REJ09B0254-0600
for transfer of 1 bit) from the end of the parity bit to the start of the next frame.
from the start bit if a parity error was detected.
the time the error signal is sampled.
communication functions are available.
Operation
Overview
Description
Transmission is in progress.
TEND is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 in TDRE.
End of transmission.
TEND is set to 1 when:
•
•
•
•
the chip is reset or enters standby mode,
the TE bit in SCSCR is 0 and the FER/ERS bit is also 0,
the C/A bit in SCSMR is 0, and TDRE = 1 and FER/ERS = 0 (normal
transmission) 2.5 etu after a one-byte serial character is transmitted, or
the C/A bit in SCSMR is 1, and TDRE = 1 and FER/ERS = 0 (normal
transmission) 1.0 etu after a one-byte serial character is transmitted.
(Initial value)
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